High-performance FPGAs take flight in microsatellites
Adam Taylor, EADS Astrium
6/1/2011 5:59 AM EDT
I am delighted to have the opportunity to present the following piece
with the kind permission of Xilinx Inc.
Utilizing Xilinx Virtex-4 devices in a U.K. CubeSat mission presents some interesting design challenges.
The UKube1 mission is the pilot mission for the U.K. Space Agency’s planned CubeSat program. CubeSats are a class of nanosatellites that are scalable from the basic 1U satellite (10 x 10 x 10 cm) up to 3U (30 x 10 x 10 cm) and beyond, and which are flown in low-earth orbit.
The typical development cost of a CubeSat payload is less than $100,000, and development time is short.
This combination makes CubeSats an ideal platform for verifying new and exciting technologies in orbit without the associated overhead or risks that would be present in flying these payloads on a larger mission.
Of course, this class of satellites can present its own series of design challenges for the engineers involved.
The EADS Astrium payload for the UKube1 mission comprises two experiments, both of which are FPGA-based. The first experiment is the validation of a patent held by Astrium on random-number generation. True random-number generation is an essential component of secure communications systems. The second experiment is the flight of a large, high-performance Xilinx Virtex-4 FPGA with the aim of achieving additional in-flight experience with this technology while gaining an understanding of the device’s radiation performance and capabilities in the low-earth orbit (LEO). Figure 1 shows the architecture of the payload.
Requirements and challenges
Designing for a CubeSat mission provides the engineers with many challenges, not least of which is the available power—there is not much of it, at 400 milliwatts on average in sunlight orbit for the UKube1. Weight restrictions come in at a shade over 300 grams for a 3U, 4.5-kg satellite. Combined with the space envelope available for a payload, these limitations present the design team with an interesting set of challenges to address if they are to develop a successful payload. The engineers must also address single-event upsets (SEUs) and other radiation effects, which can affect the performance of a device in orbit regardless of the class of satellite.
The power architecture in UKube1 provides regulated 3.3-, 5- and 12-volt supplies to each of the payloads. It is permissible to take up to 600 mA from each of these rails. However, the sunlit-orbit average must be less than 400 mW. Unfortunately, the voltages supplied are not at levels suitable to supply today’s high-performance space-grade FPGAs, which typically require 1.5 V or less to supply the core voltage. For example, the Virtex-4 space-grade device we selected for this mission, the XQR4VSX55 FPGA, requires a core voltage of 1.2 V along with supporting voltages of 2.5 and 3.3 V. The configuration PROMs needed to support the FPGA require 1.8 V.
We selected the XQR4VSX55 because it was the largest high-performance FPGA that could be accommodated within the UKube1 payload while still achieving both the footprint and power requirements. The power engineer and the FPGA engineer must give considerable thought to the power architecture to ensure all of the power constraints are achieved. Tools such as the PlanAhead™ and XPower Analyzer software are vital for the FPGA engineer to provide FPGA power budgets to the power engineer. We chose high-efficiency switching regulators for this mission to ensure we could achieve the currents required by the SX55 FPGA could be achieved.
The space available to implement the FPGA and its supporting functions is very limited, with the payload being constrained to a PC104-size printed-circuit board. However, mezzanine cards are permitted provided they do not exceed the height restrictions of 35 mm. Therefore, we developed the UKube1 payload to include a mezzanine card that contained the FPGAs, SRAM and flash memory, while the lower board contained all of the power management and conversion functionality (see Figure 2).
One of the most important aspects of this mission is to gain an understanding of the performance of the Virtex-4 device in a LEO environment. While Xilinx has hardened this FPGA for spaceflight, SEUs will still occur and affect both the configuration data and the FPGA registers, RAM and digital clock managers (DCMs). This mission therefore configures the FPGA to use most of the internal logic, RAM and DCMs. We then monitor the performance of this device using another one-time programmable hardened device, which passes performance statistics back down to the ground for analysis. Interestingly, on this mission we are less concerned with SEU- and radiation-mitigation design techniques than on ensuring that these events can be captured such that they can be detected by a monitoring FPGA, allowing for the generation of real in-flight performance statistics.
This aspect of the design presented some interesting engineering challenges. For example, an SEU could affect signals such as the DCM locked signal and incorrectly indicate that the DCM has been affected by an SEU, when in reality it has not. To counter this potential problem, the FPGA design engineers came up with a method of using counters to monitor the DCMs and make sure they are locked to the correct frequency. Should the counter freeze or increment at a different frequency, it is indicated by comparing it with the other counters, allowing for an FPGA reconfiguration if required.
U.K. Space Agency will launch UKube1 in January 2012.
The CubeSat will provide data on both of our experiments for at least the mission lifetime of one year. This mission will demonstrate the suitability of high-performance FPGAs for use in LEO missions and microsatellite architectures as well as hopefully allowing the use of high-performance FPGAs in other missions of longer duration.
The UKube1 is expected to be just the first of a national CubeSat program in the U.K.
The architecture developed for UKube1 lends itself to adaptation for use on future missions to gain further understanding of, and experience in, using large, high-performance FPGAs in orbit. Potential adaptations for the next mission would include a demonstration of in-orbit partial reconfiguration and in-orbit readback and verification of the device configuration. Unfortunately, due to the time scales involved in the development of UKube1, these experiments could not be incorporated on this maiden voyage.
The UKube1 architecture using the Xilinx Virtex-4 family of devices also lends itself to evolution into a system-on-chip-based controller that could serve as a micro- or nanosatellite mission controller.
About the author:
Adam Taylor is Principal Engineer at EADS Astrium