Xilinx賽靈思

Xilinx, Micron demo FPGA, RLDRAM 3 memory interoperability

三月 23, 2012
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Xilinx, Micron demo FPGA, RLDRAM 3 memory interoperability

Posted:16 Mar 2012

http://www.eetasia.com/ART_8800663232_499485_NP_2c2b5a2b.HTM?8800091821&8800663232&click_from=8800091821,8723946550,2012-03-16,EEOL,ARTICLE_ALERT#

Xilinx Inc. and Micron Technology Inc. have demonstrated the first t public hardware FPGA interfacing with RLDRAM 3 memory. RLDRAM 3 is a new and emerging memory standard for high-end networking applications such as packet buffering and inspection, linked lists, and lookup tables. It enables 40G and 100G networking systems that require higher speed, higher density, lower power and lower latency.

Operating with Virtex-7 and Kintex-7 FPGAs at data rates up to 1,600Mb/s, Micron’s RLDRAM 3 memory combines high density, high bandwidth and fast SRAM-like random access to enable a 60 percent higher data rate and memory bandwidth compared to previous generation (Virtex-6 FPGAs/RLDRAM2 memory standard) memories, the companies said.

Virtex-7 and Kintex-7 FPGAs are designed with the necessary IO standards and architectural components for optimal interfacing with RLDRAM 3, providing a significant boost to system performance for high-performance wireless and wired networking systems. RLDRAM 3 memory uses innovative circuit design to minimize the time between the beginning of an access cycle and the instant that the first data is available. Ultra-low bus turnaround time enables higher sustainable bandwidth with near-term balanced read-to-write ratios.

"The new RLDRAM 3 interface is ideal for Xilinx and Micron’s mutual customers in the high-end networking space who require higher speed, higher density, lower power and lower latency," said Derek Curd, technical marketing manager at Xilinx. "The RLDRAM 3 hardware demonstration shows how we’re able to achieve a much more efficient transfer of network data."

Hardware demonstrations of the Xilinx RLDRAM 3 Memory interface IP core are available now with user configurable IP cores available in ISE Design Suite 13.4 in September 2012.

Qualified Micron RLDRAM 3 memory devices are currently available in x18 and x36 organizations across all speed grades from 800 to 1,066MHz.

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Xilinx Announces ISE Design Suite 13.4 Further Extending 7 Series FPGA Support and Design Productivity

一月 24, 2012
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Xilinx Announces ISE Design Suite 13.4

Further Extending 7 Series FPGA Support and Design Productivity

http://www.prnewswire.com/news-releases/xilinx-announces-ise-design-suite-134-further-extending-7-series-fpga-support-and-design-productivity-137555938.html

Latest release includes the New MicroBlaze Micro Controller System, Enhanced Debug with 2D Eye Scan and Partial Reconfiguration Support for Artix-7 and Virtex-7 XT FPGAs

XILINX LOGO</p> <p>Xilinx is the worldwide leader of programmable logic solutions. (PRNewsFoto/Xilinx)<br /> SAN JOSE, CA UNITED STATES<br />

SAN JOSE, Calif., Jan. 18, 2012 /PRNewswire/ — Xilinx, Inc. (NASDAQ: XLNX) today released ISE® Design Suite 13.4, which provides public access to the MicroBlaze™ Micro Controller System (MCS), new RX Margin Analysis and debug capabilities for the 28nm 7 Series FPGAs and partial reconfiguration support for the Artix™-7 family and Virtex®-7 XT devices.

(Logo: http://photos.prnewswire.com/prnh/20020822/XLNXLOGO)

MicroBlaze MCS Simplifies Microcontroller-based Designs

MicroBlaze MCS, new to the Xilinx® LogiCORE™ IP core offering, provides a turnkey microcontroller solution to Xilinx customers. It includes the MicroBlaze processor, local memory for program and data storage, as well as tightly coupled GPIO, timers, interrupt controllers and other standard peripherals.

MCS is supported across a broad range of Xilinx FPGA families, and is pre-configured for easy deployment by hardware developers. Software developers will find familiar tools including the Xilinx Software Development Kit (SDK), command line gcc, Xilinx Microprocessor Debugger (XMD) and the same standard MicroBlaze API used by larger processor configurations.  Hardware developers will appreciate that the MicroBlaze processor and all Xilinx embedded IP cores are now supported with the Synopsys VCS simulator in addition to Cadence, Mentor and Xilinx simulation solutions. The MicroBlaze MCS is included in all ISE Design Suite Editions, ISE WebPACK and is compatible with AutoESL™ high-level synthesis tool v2011.4.

New RX Margin Analysis Tool

The ChipScope™ Pro tool, available in the ISE 13.4 release, now provides an RX Margin Analysis tool to help engineers optimize signal quality and lower the bit error ratio (BER) on their designs. The RX Margin Analysis tool uses 2-dimensional statistical Eye Scan algorithms to interactively characterize and optimize channel quality in real time, or during post-run processing.

4th Generation Partial Reconfiguration

Partial reconfiguration support for Artix-7 and Virtex-7 XT FPGAs is now available in the PlanAhead™ tool. Partial reconfiguration dynamically modifies logic blocks while the remaining logic operates without interruption. This means designers can use Artix-7 and Virtex-7 XT devices to build flexible systems that are able to swap functions and perform remote updates while operational. Partial reconfiguration also allows designers to reduce costs and design size by taking advantage of time-multiplexing that ultimately leads to reduced board space and minimizes bitstream storage because smaller, or fewer, devices can be utilized. Smaller and fewer devices can also lead to reductions in system power, while swapping out power hungry tasks can minimize the FPGA’s dynamic power consumption. This marks the first time Xilinx is offering partial reconfiguration for an entire generation of FPGA families from low-cost to high-end.

"With hardware designs increasingly using more point-to-point buses, at faster speeds and sending larger data packets, it is becoming more important for design engineers to pay close attention to the quality, error rates and margins that such designs require," said Tom Feist, Senior Director of Software and Tools Marketing at Xilinx. "Increasing designer productivity continues to be the top focus for Xilinx. ISE Design Suite 13.4 further extends and simplifies our development tools to ensure their ease of use and support in deploying our entire 7 series FPGA families in these types of designs."

Extends Support for 7 Series FPGAs

ISE Design Suite 13.4 is the first public release supporting the Artix-7 and Virtex-7 XT FPGA families.

The Artix-7 FPGA delivers the lowest power and lowest cost to address high-volume markets including: consumer 3DTV, multifunction printers, digital SLR cameras, automotive driver assistance and infotainment, low power handheld communications, medical endoscopes and handheld ultrasound devices and industrial system monitor and control. With Agile Mixed Signal (AMS) capabilities, included in all 28nm Xilinx devices, designers have the industry’s most flexible general purpose analog interface for customizing a wide variety of applications, from simple control and sequencing to more signal processing intensive tasks like linearization, calibration, and filtering.

Virtex-7 XT devices offer the highest processing bandwidth with high performance transceivers, digital signal processing (DSP) and BRAM. These devices integrate an unprecedented up to 96 10G Base KR backplane-capable serial transceivers, provide 5.3 TMACs of DSP, 67 Mbits of internal memory and more than 1M logic cells. The Virtex-7 XT family utilizes Xilinx’s revolutionaryStacked Silicon Interconnect (SSI) technology, allowing multiple die to be combined in a single chip, and provides a 100x improvement in inter-die bandwidth per watt compared to multi-chip approaches.

PlanAhead Tool Extends User Productivity

The Xilinx ISE PlanAhead Design and Analysis Tool is a comprehensive development environment for design creation, analysis, planning and implementation. The PlanAhead tool accelerates time to production with a unique integrated front-to-back environment that includes design analysis at each phase of the design cycle – RTL development, IP integration, verification, synthesis and place and route. The end result is rapid convergence on power consumption, resource utilization and performance with fewer time-consuming design iterations. Up front design analysis and design preservation flows that ensure timing from run to run are critical for customers targeting the new 7 series devices.

The PlanAhead tool now provides public access for Xilinx 7 series FPGAs with productivity improvements to assist users in closing their designs, intelligent clock gating to reduce power, team design flows and fifth-generation partial reconfiguration technology now offered for Artix-7 FPGAs and Virtex-7 XT FPGAs to enable fewer or smaller devices, reduce power and improve system upgradability.

Availability and Pricing

ISE Design Suite 13 is available now for all ISE Editions and list priced starting at $2,995 for the Logic Edition and now supports 32 and 64 bit Windows 7 operating systems.

Customers can download full-featured 30-day evaluation versions at no charge from the Xilinx web site.

Please visit the ISE Design Suite 13 website to get started today with the ISE Design Suite 13 software release or for more information about the power and cost-saving design methodologies and productivity innovations introduced in ISE Design Suite 13.

Silica Xynergy Board – STM32 meets Spartan-6

十一月 18, 2011
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Silica Xynergy Board – STM32 meets Spartan-6

http://www.silica.com/products/highlight/product/silica-xynergy-board-stm32-meets-spartan-6.html

silica xilinx ST xynergy board iconThe Xynergy Board from SILICA combines an ARM Cortex-M3 based STMicroelectronics STM32F217 controller with a Xilinx Spartan-6 low-cost FPGA (XC6SLX16) in one design.

There are numerous development tools for either ARM Cortex-M microcontrollers or FPGA kits, but this is the first module in the market that merges both technologies on one board, although it is absolutely common to have a microcontroller next to an FPGA, performing tasks that cannot be integrated in the FPGA in a cost-effective way.

High costs for the adequate IP cores and for the additionally needed resources in the FPGA very often require an implementation in favor of a two-chip solution. Particularly the use of standard communication interfaces like Ethernet, USB and CAN are in most cases cheaper and easier to implement on a microcontroller.

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Xilinx Virtex-7 FPGA Demonstration

七月 5, 2011
By

YouTube 首頁First Xilinx Virtex-7 FPGA Demonstration

video

http://www.youtube.com/watch?v=hWyV09Ffo1U&feature=youtube_gdata

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High-performance FPGAs take flight in microsatellites

六月 17, 2011
By

High-performance FPGAs take flight in microsatellites

Adam Taylor, EADS Astrium

6/1/2011 5:59 AM EDT

Editor’s Note:

http://www.eetimes.com/design/military-aerospace-design/4216480/High-performance-FPGAs-take-flight-in-microsatellites?cid=NL_CommsDesign&Ecosystem=communications-design

I am delighted to have the opportunity to present the following piece

from the second quarter 2011 issue of the Xcell Journal,

with the kind permission of Xilinx Inc.

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Utilizing Xilinx Virtex-4 devices in a U.K. CubeSat mission presents some interesting design challenges.

The UKube1 mission is the pilot mission for the U.K. Space Agency’s planned CubeSat program. CubeSats are a class of nanosatellites that are scalable from the basic 1U satellite (10 x 10 x 10 cm) up to 3U (30 x 10 x 10 cm) and beyond, and which are flown in low-earth orbit.

The typical development cost of a CubeSat payload is less than $100,000, and development time is short.

This combination makes CubeSats an ideal platform for verifying new and exciting technologies in orbit without the associated overhead or risks that would be present in flying these payloads on a larger mission.

Of course, this class of satellites can present its own series of design challenges for the engineers involved.
The EADS Astrium payload for the UKube1 mission comprises two experiments, both of which are FPGA-based. The first experiment is the validation of a patent held by Astrium on random-number generation. True random-number generation is an essential component of secure communications systems. The second experiment is the flight of a large, high-performance Xilinx Virtex-4 FPGA with the aim of achieving additional in-flight experience with this technology while gaining an understanding of the device’s radiation performance and capabilities in the low-earth orbit (LEO). Figure 1 shows the architecture of the payload.


(Click on image to enlarge)

Requirements and challenges
Designing for a CubeSat mission provides the engineers with many challenges, not least of which is the available power—there is not much of it, at 400 milliwatts on average in sunlight orbit for the UKube1. Weight restrictions come in at a shade over 300 grams for a 3U, 4.5-kg satellite. Combined with the space envelope available for a payload, these limitations present the design team with an interesting set of challenges to address if they are to develop a successful payload. The engineers must also address single-event upsets (SEUs) and other radiation effects, which can affect the performance of a device in orbit regardless of the class of satellite.
The power architecture in UKube1 provides regulated 3.3-, 5- and 12-volt supplies to each of the payloads. It is permissible to take up to 600 mA from each of these rails. However, the sunlit-orbit average must be less than 400 mW. Unfortunately, the voltages supplied are not at levels suitable to supply today’s high-performance space-grade FPGAs, which typically require 1.5 V or less to supply the core voltage. For example, the Virtex-4 space-grade device we selected for this mission, the XQR4VSX55 FPGA, requires a core voltage of 1.2 V along with supporting voltages of 2.5 and 3.3 V. The configuration PROMs needed to support the FPGA require 1.8 V.
We selected the XQR4VSX55 because it was the largest high-performance FPGA that could be accommodated within the UKube1 payload while still achieving both the footprint and power requirements. The power engineer and the FPGA engineer must give considerable thought to the power architecture to ensure all of the power constraints are achieved. Tools such as the PlanAhead™ and XPower Analyzer software are vital for the FPGA engineer to provide FPGA power budgets to the power engineer. We chose high-efficiency switching regulators for this mission to ensure we could achieve the currents required by the SX55 FPGA could be achieved.
The space available to implement the FPGA and its supporting functions is very limited, with the payload being constrained to a PC104-size printed-circuit board. However, mezzanine cards are permitted provided they do not exceed the height restrictions of 35 mm. Therefore, we developed the UKube1 payload to include a mezzanine card that contained the FPGAs, SRAM and flash memory, while the lower board contained all of the power management and conversion functionality (see Figure 2).

Radiation effects
One of the most important aspects of this mission is to gain an understanding of the performance of the Virtex-4 device in a LEO environment. While Xilinx has hardened this FPGA for spaceflight, SEUs will still occur and affect both the configuration data and the FPGA registers, RAM and digital clock managers (DCMs). This mission therefore configures the FPGA to use most of the internal logic, RAM and DCMs. We then monitor the performance of this device using another one-time programmable hardened device, which passes performance statistics back down to the ground for analysis. Interestingly, on this mission we are less concerned with SEU- and radiation-mitigation design techniques than on ensuring that these events can be captured such that they can be detected by a monitoring FPGA, allowing for the generation of real in-flight performance statistics.
This aspect of the design presented some interesting engineering challenges. For example, an SEU could affect signals such as the DCM locked signal and incorrectly indicate that the DCM has been affected by an SEU, when in reality it has not. To counter this potential problem, the FPGA design engineers came up with a method of using counters to monitor the DCMs and make sure they are locked to the correct frequency. Should the counter freeze or increment at a different frequency, it is indicated by comparing it with the other counters, allowing for an FPGA reconfiguration if required.

Future developments
U.K. Space Agency will launch UKube1 in January 2012.

The CubeSat will provide data on both of our experiments for at least the mission lifetime of one year. This mission will demonstrate the suitability of high-performance FPGAs for use in LEO missions and microsatellite architectures as well as hopefully allowing the use of high-performance FPGAs in other missions of longer duration.

The UKube1 is expected to be just the first of a national CubeSat program in the U.K.

The architecture developed for UKube1 lends itself to adaptation for use on future missions to gain further understanding of, and experience in, using large, high-performance FPGAs in orbit. Potential adaptations for the next mission would include a demonstration of in-orbit partial reconfiguration and in-orbit readback and verification of the device configuration. Unfortunately, due to the time scales involved in the development of UKube1, these experiments could not be incorporated on this maiden voyage.

The UKube1 architecture using the Xilinx Virtex-4 family of devices also lends itself to evolution into a system-on-chip-based controller that could serve as a micro- or nanosatellite mission controller.

About the author:


Adam Taylor is Principal Engineer at EADS Astrium

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Meet Aggressive Power Budgets with 7 Series FPGAs

六月 17, 2011
By

Meet Aggressive Power Budgets with 7 Series FPGAs

Webcast Dates & Times:

Tuesday June 14th, 2011
11:00 AM PDT / 2:00 PM EDT / 18:00 GMT

Thursday June 16th, 2011
8:00 AM PDT / 11:00 AM EDT / 15:00 GMT

This webinar will explore how engineers can use Xilinx® 7 series FPGAs to meet the tight power budgets of their latest electronic system designs. Through a unified and scalable architecture and a versatile 28nm High Performance Low Power (HPL) process, Xilinx is able to deliver a full range of power-efficient FPGA product families for today’s demanding applications. Attendees will learn how 7 series FPGA power and performance advantages can be applied to their unique designs through several in-depth case study examples.

During this Webcast you will learn:

  • How Xilinx, through a versatile 28nm High Performance Low Power (HPL) process and a unified and scalable architecture, is able to deliver a full range of power-efficient FPGA product families for today’s demanding applications
  • How designers can leverage the latest Xilinx tools, design techniques, product features, and device options to achieve power-optimized designs while meeting critical performance targets

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Enabling FPGA Plug-and-Play Design with the AXI-4 Common Interconnect

三月 28, 2011
By

 

http://www.avnetondemand.com/?vid=1084&cid=53

Enabling FPGA Plug-and-Play Design with the AXI-4 Common Interconnect

This video offers details of Xilinx support for the AXI-4 Common Interconnect and highlights the benefits of increased designer productivity, greater IP availability, and extended flexibility to achieve performance and system goals.

Using the Xilinx Targeted Design Platforms to illustrate these benefits, Xilinx technical experts describe how support for the AXI-4 Common Interconnect is the cornerstone for the move to FPGA Plug-and-Play design.

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Xilinx Ships World’s First 28nm FPGA Device and Demonstrates Application Development Platform for Next Generation Systems

三月 22, 2011
By

 

Xilinx Ships World’s First 28nm FPGA Device

and Demonstrates Application Development Platform

for Next Generation Systems

http://www.prnewswire.com/news-releases/xilinx-ships-worlds-first-28nm-fpga-device-and-demonstrates-application-development-platform-for-next-generation-systems-118273964.html

First Kintex-7 K325T FPGAs Ship to Customers for their Next Generation Systems

SAN JOSE, Calif., March 18, 2011 /PRNewswire/ — Xilinx, Inc. (Nasdaq: XLNX) today announced the beginning of the 7 series FPGA rollout with shipment of the first Kintex™-7 K325T Field Programmable Gate Array (FPGA), marking the industry’s fastest product rollout of next generation programmable logic devices built with 28nm technology. Kintex-7 FPGAs are built to provide optimal price performance at the lowest power to meet requirements for key applications.  At the same time, the Kintex-7 FPGA family leverages the unified architecture shared across the 7 series, 28nm device families to enable customers to begin FPGA development now for designs that may ultimately migrate to Artix™-7 and Virtex®-7 FPGAs.

(Photo:  http://photos.prnewswire.com/prnh/20110318/SF68119)

(Logo:  http://photos.prnewswire.com/prnh/20020822/XLNXLOGO)

The Kintex-7 devices are offered in conjunction with the Xilinx® ISE® Design Suite 13, AMBA® 4 Advanced Extensible Interface (AXI) bus protocol-compliant IP, and targeted reference designs. All of these Targeted Design Platform components run on the new Kintex-7 FPGA KC705 evaluation board currently being demonstrated for customers so that designers can evaluate the power consumption, performance, and capabilities of the new Kintex-7 K325T devices. Xilinx delivered the new devices in less than 90 days from tape-out by leveraging TSMC’s 28nm High-Performance, Low-Power (HPL) process that relies on proven design and manufacturing methodologies. You can see a video demonstration of the device on YouTube athttp://www.youtube.com/watch?v=abmQPQ6Eiww.

"The optimal price performance available in the Kintex-7 family makes it an ideal fit for our next generation visualization products," said Eric Wogsberg, CEO of Jupiter Systems. "The new 7 series unified architecture also allows us to start developing products today that use Kintex-7 and later upgrade to more advanced products that will use the Virtex-7 FPGA family.  This lowers our development cost and allows us to build scalable solutions."

"As the world’s fastest-growing oscilloscope vendor, we’re continually looking for technology that offers higher performance, lower power, with high-speed transceivers.  We’re in a unique position of offering scopes with unparalleled real-time 32GHz analog bandwidth and sampling scopes for high-speed serial debug and characterization, as well as developing instruments that rely on capable high-speed serial I/O.  We’re excited to be one of the first customers to be shipped a Kintex-7 K325T FPGA due to its combination of performance, low power, and serial capabilities. The price performance available in the Kintex-7 family makes it compelling for next generation test equipment," said Joel Woodward, high-performance oscilloscope planner, Agilent Technologies. "We’ve used Xilinx devices in multiple generations of oscilloscope where we are driven to lower development cost and build scalable test and measurement solutions."

Industry’s First 28nm Targeted Design Platform Accelerates 7 Series FPGA Development

With the shipping of the first Kintex-7 FPGAs to customers, Xilinx is also introducing the industry’s first 28nm Targeted Design Platform that combines the Kintex-7 K325T FPGA, ISE development tools, AXI 4 compliant IP, and an initial version of the base targeted reference design running on the Kintex-7 FPGA KC705 evaluation board.  This new 7 series targeted design platform allows customer to immediately begin evaluation of the low power, higher performance, and advanced features available in the Kintex-7 FPGA family including Artix-7 and Virtex-7 FPGAs. Designers and engineers have an easy to use, flexible FPGA platform as an alternative to inflexible and slow-to-develop ASIC or ASSP-based silicon solutions.

"In parallel with the development of the first 28nm FPGAs Xilinx refined the Xilinx ISE design tools to enable faster runtimes, enable designs that use up to 2 million logic cells, and shorten migration of AXI protocol-compliant IP initially developed in Virtex-6 and Spartan®-6 FPGAs to the 7 series from weeks to hours," said Bruce Kleinman, Corporate Vice President of Platform Marketing at Xilinx. "As a result of these efforts Xilinx has been able to bring up the first 7 series targeted design platform within hours with a fully operational design that demonstrates the key benefits of the 7 series devices."

Kintex-7 FPGAs

The Kintex-7 K325T device is the first FPGA in this class to deliver the highest number of channels per dollar at less than 12 watts of power for LTE wireless radio cards and next generation wireless base stations.  Kintex-7 FPGAs provide the optimized price performance required for flat panel displays, ultrasound equipment and many other applications and includes high-bandwidth, low jitter serial transceivers to address price sensitive wired communication applications.  The Kintex-7 K325T FPGA is the first of 28 devices that make up the 7 series FPGA that includes the Artix-7 and Virtex-7 FPGA families.

About Xilinx 7 Series FPGAs 

Xilinx 7 series FPGAs are built on the industry’s lowest power and only unified FPGA architecture that scales across low-cost and ultra high-end families while enabling the fastest product rollout of 350 speed grade, temperature range, and package combinations. The 28nm Artix-7, Kintex-7, and Virtex-7 families extend Xilinx’s Targeted Design Platform strategy by combining breakthrough innovations in power efficiency, performance capacity, and price performance with unprecedented levels of scalability and productivity to make programmable logic more accessible to a broader community of users, end markets and applications. 7 series FPGAs utilize Stacked Silicon Interconnect technology to deploy the world’s highest density 2 million logic cell FPGA, the Virtex-7 2000T device. Each 7 series device is built with a mix of features including dual 12-bit, 1 MSPS general purpose analog-to-digital converters, transceivers, DSP blocks, on-chip memory and much more. For more information on Xilinx 7 series FPGAs and Xilinx 28nm Targeted Design Platforms, visit http:/www.xilinx.com/7.

Availability

Kintex-7 K325T FPGA initial samples are shipping now and order entry for the Kintex-7 FPGA base Targeted Design Platform that uses the Kintex-7 FPGA KC705 evaluation board will open in Q4 2011.  Customers can arrange a demonstration of an advanced version of the platform now by contacting their local Xilinx representative.

The Virtex-7 485T FPGA and the 2 million logic cell 2000T will begin initial sampling in August and November of 2011, respectively.  Artix-7 FPGA initial samples will ship first quarter of 2012. Customers can start designing today to take advantage of the price, performance, and low power consumption advantages offered by the 7 series FPGAs using the ISE Design Suite 13. Customers can download a full-featured 30-day evaluation versions of ISE Design Suite 13 at no charge fromwww.xilinx.com/tools/designtools.htm.

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Designing Cost-effective, Greener LTE Basestations with Xilinx FPGAs

三月 9, 2011
By

 

Designing Cost-effective, Greener LTE Basestations with Xilinx FPGAs

Webcast

Exponential growth in mobile data has fuelled enormous interest in 4G wireless technology such as LTE. However, the increased processing constraints placed provide a significant challenge in meeting the dual imperatives of base station cost and power reduction. This webcast will describe how Xilinx FPGAs and IP help resolve these issues, providing a scalable and reconfigurable platform for base station development.

During this Webcast you will learn:

  • How to future-proof designs through the use of a scalable, reconfigurable architecture
  • How to reduce cost, dissipation and form factor
  • How parallelism of Xilinx FPGAs can help differentiate products through the implementation of advanced receiver techniques

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Synopsys, Xilinx offer FPGA prototyping manual

三月 3, 2011
By

Synopsys, Xilinx offer FPGA prototyping manual

http://www.eetimes.com/electronics-news/4213693/Synopsys–Xilinx-offer-FPGA-prototyping-manual?cid=NL_EETimesDaily

3/2/2011 12:31 PM EST

Synopsys and Xilinx have made available the FPGA-Based Prototyping Methodology Manual, a practical guide to using FPGAs as a platform for SoC development. SAN FRANCISCO—EDA and IP vendor Synopsys Inc. and programmable logic vendor Xilinx Inc. have made available the FPGA-Based Prototyping Methodology Manual (FPMM), a practical guide to using FPGAs as a platform for system-on-chip (SoC) development, the companies said Wednesday (March 2).

According to the companies, the FPMM includes design and verification expertise contributed by engineering teams from several companies, including Texas Instruments Inc., STMicroelectronics NV, Freescale Seminductor Inc. and Nvidia Corp.

Each of these engineering teams has employed FPGA-based prototyping to accelerate complex ASIC and SoC development projects, according to Synopsys (Mountain View, Calif.) and Xilinx (San Jose, Calif.).

The manual covers all aspects of FPGA-based prototyping, including understanding the challenges and benefits of prototyping, the implementation of a SoC design in FPGA and its use for software and system validation, the companies said. The manual is authored by Doug Amos and René Richter of Synopsys and Austin Lesea of Xilinx.

More information about the book, including instructions on how to purchase a copy through Amazon.com and downloading a free eBook version, are available on Synopsys’ website.

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