Microcontroller news – STM32 F3 series – November 2012
To optimize code execution time, STM32F302/303/313 devices have 8 Kbytes of SRAM mapped to the instruction bus as core coupled memory (CCM-SRAM).
Critical routines loaded in the 8-Kbyte CCM at startup can be completed at full speed with zero wait states, achieving 90 Dhrystone MIPS at 72 MHz. A
This compares with 63 DMIPS when executing from Flash or SRAM; equivalent to a 43% performance increase for critical routines.
It can be used to speed up execution of control loops in motor control and digital power supplies or to reduce energy consumption by staying in run mode for less time.
The 8-Kbyte CCM-SRAM can also be used for data storage with no performance trade-offs.
CCM-SRAM is provided with a parity bit for safer behavior.