DCD’s DT8051 powerful, tiny 8-bit CPU


DCD’s DT8051 powerful, tiny 8-bit CPU


Clive Maxfield

11/6/2012 10:47 AM EST


The DT8051 from Digital Core Design (DCD) is an area-optimized tiny soft core of a single chip 8-bit embedded microcontroller, based on the most popular 8051 MCU.

For many applications this IP core offers an excellent solution,

especially when you consider that even a stripped-down 32-bit ARM Cortex-M0 requires more than 10000 gates.

"In terms of the cost an area of silicon-proven DT8051, not just other 8-bit MCUs, but also a 32-bit processor licensing comes close,"

says Tomek Krzyzak, the Vice President of Digital Core Design. 


"Moreover, our DT8051 can run in very small FPGA devices or can be just a tiny fragment of a Sys-tem-on-Chip ASIC – as the old saying goes: small is beautiful."

A very low gate count and small silicon area allows the core to run at up to 300 MHz using the Hynix 0.18 library

(this is equivalent in performance to the original 80C51 being clocked at 2400 MHz).

The DT8051 soft core is 100% binary-compatible with industry-standard 8051 8-bit microcontrollers, but in comparison to its ancestor,

DCD’s IP core has a very low gate count architecture, requiring only 6,650 ASIC gates for the complete system with peripherals and the DoCD on-chip debugger.

But small size would not mean anything without appropriate performance.


"The DT8051 could be named a ‘mighty power,’" says Piotr Kandora, a VP & Director of R&D at DCD. "

The Dhrystone 2.1 benchmark program runs exactly 8.1 times faster than the original 80C51 at the same frequency.

The performance results are more than 2 times higher than the nearest competitive designs."

The DT8051 includes a 2-wire DoCD on-chip debugger (TTAG),

up to eight external interrupt sources, an advanced Power Management Unit, Timers 0&1, I/O bit addressable Ports,

full duplex UART and interface for external SFR.

The DT8051 is delivered with fully automated test bench and complete set of tests,

allowing easy package validation, at each stage of SoC design flow.

Click Here for more information.




發佈留言必須填寫的電子郵件地址不會公開。 必填欄位標示為 *