Xilinx, Micron demo FPGA, RLDRAM 3 memory interoperability
Posted:16 Mar 2012
Xilinx Inc. and Micron Technology Inc. have demonstrated the first t public hardware FPGA interfacing with RLDRAM 3 memory. RLDRAM 3 is a new and emerging memory standard for high-end networking applications such as packet buffering and inspection, linked lists, and lookup tables. It enables 40G and 100G networking systems that require higher speed, higher density, lower power and lower latency.
Operating with Virtex-7 and Kintex-7 FPGAs at data rates up to 1,600Mb/s, Micron’s RLDRAM 3 memory combines high density, high bandwidth and fast SRAM-like random access to enable a 60 percent higher data rate and memory bandwidth compared to previous generation (Virtex-6 FPGAs/RLDRAM2 memory standard) memories, the companies said.
Virtex-7 and Kintex-7 FPGAs are designed with the necessary IO standards and architectural components for optimal interfacing with RLDRAM 3, providing a significant boost to system performance for high-performance wireless and wired networking systems. RLDRAM 3 memory uses innovative circuit design to minimize the time between the beginning of an access cycle and the instant that the first data is available. Ultra-low bus turnaround time enables higher sustainable bandwidth with near-term balanced read-to-write ratios.
“The new RLDRAM 3 interface is ideal for Xilinx and Micron’s mutual customers in the high-end networking space who require higher speed, higher density, lower power and lower latency,” said Derek Curd, technical marketing manager at Xilinx. “The RLDRAM 3 hardware demonstration shows how we’re able to achieve a much more efficient transfer of network data.”
Hardware demonstrations of the Xilinx RLDRAM 3 Memory interface IP core are available now with user configurable IP cores available in ISE Design Suite 13.4 in September 2012.
Qualified Micron RLDRAM 3 memory devices are currently available in x18 and x36 organizations across all speed grades from 800 to 1,066MHz.
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