How ARM’s Cortex-A7 Beats the A15
Peter Clarke, European News Director
7/19/2013 07:45 AM EDT
ARM’s Cortex-A series of processors has now divided into three tiers associated with low, medium, and high performance.
The high tier is optimized for performance, and the low tier is optimized for stripped-down power efficiency at lower absolute performance levels, all in support of the big-little and heterogeneous multicore processing.
At the 32-bit level these three tiers feature the A7, the A12, and A15, and the 64-bit level is represented by the Cortex-A57.
The high efficiency processor is the Cortex-A53.
Does that mean the market should expect a series of mid-range parts in the Cortex-A5X series and going forward? Yes although ARM executives that I recently met with were also keen to keep their marketing powder dry. Does it mean that ARM is going to start implementing a big-medium-little processor core strategy?
In the short term probably not, but I would like to assign that discussion for another day.
But what ARM engineers did show me at a recent analysts’ conference is that relative performance of the Cortex-A7 and A15 differs by a factor of two or three depending on workload and implementation. Now, when you add that to the fact that the Cortex-A7 occupies about one quarter or one fifth of the die area and consumes one quarter to one fifth of the power, things become interesting (see chart below).
Three tiers of processor cores with performance
going up and to the right over time.
To reiterate: With a Cortex-A15, at five times the area and five times the power consumption, you can get two or three times the performance of the Cortex-A7.
So why wouldn’t you replace any Cortex-A15 cores with four Cortex-A7s?
You would get more raw performance at about the same power consumption and in the same die area.
The reason, of course, depends on considering single-thread performance, but still it makes you think about the implications for multicore SoC architectures.
When I put my observation to Nandan Nayampally, vice president of product marketing for application processors at ARM, he said: "Yes four A7s is more performance than one A15 for multi-threaded applications, but in mobile, single-threaded peak performance is also important." Point made.
But Nayampally conceded that the stripped-down "little" cores do have a vital role to play in future SoCs. He admitted that some SoCs may depend substantially on little cores. "So you will see things like networking SoCs with a couple of A15s or A57s and a lot of A7s or A53s.
This then moves to generalize further to A7/A12/A15 and other resources, and an operating system governor will make allocations."
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