ST-MRAM gets practical


ST-MRAM gets practical

J.M. Slaughter, N.D. Rizzo, et al., Everspin Technologies Inc.

4/8/2013 1:46 PM EDT

Editor’s note: This work was first presented at the 2012 IEEE International Electron Devices Meeting (IEDM) and appears here courtesy of the IEEE. For more information about IEDM 2013 (Washington DC; December 9-11), click here.

We review key properties for commercial ST-MRAM circuits, discuss the challenges to achieving the many performance and scaling goals that are being addressed in current development around the world, recent results in the field, and present first results from a new, fully-functional 64-Mb, DDR3, ST-MRAM circuit.

Spin-torque magnetoresistive random access memory (ST-MRAM) is being developed for a number of purposes: extending MRAM technology to densities beyond those achieved with toggle switching, enabling embedded nonvolatile memory with a small cell size, and as an eventual successor to high-density DRAM with the potential to solve extreme scaling problems.

Figure 1 shows typical memory cells for toggle MRAM, the field-switched technology in production today at Everspin, and ST-MRAM, both with a one magnetic tunnel junction (MTJ) and a pass transistor per cell. In both cells the data is stored in the magnetic state of the MTJ and read back by sensing the corresponding resistance of the MTJ. In toggle MRAM, the free layer magnetization is switched by a magnetic field created by current pulses through adjacent write lines and the transistor only passes the read current. This separation of read and write current paths has advantages, but scaling of field-switched MRAM is generally difficult. In ST-MRAM a write current is passed directly through the MTJ that switches the free layer magnetization by spin torque transfer [1,2], creating the additional requirement that the pass transistor be sized to support the required current.

Figure 1: Cell diagrams of a) toggle MRAM

and b) 1T-1MTJ ST-MRAM under development.

toggle MRAM switches with magnetic fields from current in nearby lines; ST-MRAM uses spin torque from the spin-polarized tunneling current.

The basic scaling argument for ST-MRAM is illustrated in figure 2. If the critical current density for spin-torque switching (Jc) can be held constant, then compatibility with a minimum-size transistor improves with decreasing feature size, λ, since the critical current for switching, Ic, will scale as λ2 while the saturation current, Id-sat, of a minimum-size transistor scales as λ. However, there are a number of challenges to achieving this ideal behavior, some of which are described below.

Figure 2: Ic and associated ISW calculated for spin-torque switching of MTJ arrays assuming Jc can be held constant while scaling. Id-sat is assumed to be ~700 μA per μm of width, independent of node.

Significant results from several ST-MRAM demonstration circuits have been published, beginning with a 4-kb test vehicle in 2005 [3] followed by many others including: a 2-Mb circuit and device data in 2007 [4], statistical data on 4 kb integrated arrays with 70×210 nm2 bits [5] and devices with perpendicular magnetization [6] in 2008, arrays integrated with 54-nm CMOS technology [7] and perpendicular bit switching in 2010 [8], and single-bit data for 20nm diameter perpendicular devices in 2011 [9]. The continuous improvement reported in these papers, and many others, reflects significant innovation and progress toward the use of spin-torque switching in products.

Key properties of ST-MRAM devices
One key requirement for a fully functional ST-MRAM is achieving a critical voltage (Vc) distribution that is well separated from the tunnel barrier breakdown distribution.

For a switching voltage Vsw that reliably switches Mbits without breakdown fails, at least 6σ separation is needed from Vsw to both distributions as shown in figure 3.

Figure 3: An illustration of key distributions in ST-MRAM arrays. The bit switching voltage (Vsw) must be separated from the Vc the Vbd distributions. To avoid disturbs, the read voltage Vread must not overlap Vc. Narrow distributions are critical for error-free operation.

In practice more is needed to allow for write voltage variation and time-dependent dielectric breakdown (TDDB) effects. Since the voltage required to breakdown a dielectric layer (Vbd) is reduced as the time at bias is increased, repeated cycling of the bias results in a shift of the breakdown distribution to the left, reducing separation from the Vc distribution. This TDDB effect is quite significant over the life of a part and extra single-cycle separation must be engineered into the devices to achieve the desired endurance. Figure 4 shows experimental data for integrated arrays with over 30σ separation.

A low Jc is required for low Vc and also minimizes Ic, allowing a smaller pass transistor. Smaller MTJ area A also reduces Ic but measures must be taken to maintain data retention since energy barrier to switching (Eb) is approximately proportional to A. We have determined experimentally that Eb for in-plane magnetization is optimum for shaped bits with aspect ratio near 3.

Figure 4: Probability of bit switching (AP-to-P) and tunnel barrier breakdown vs. applied voltage (Vapplied) for bits with the optimized CoFeB-based free layer measured in kb ST-MRAM arrays integrated with CMOS with pulse duration tp≈100ns. The separation between the switching and breakdown is >30σ.

Small increases in thickness can increase Eb at the expense of somewhat higher VC as shown experimentally in figure 5. An increase in saturation magnetization of only 10% can dramatically increase the energy barrier, for example from 60 kBT to 80 kBT. Since data retention time (τ) is exponentially dependent on Eb, the mean value of τ increases by 8 orders of magnitude with this small magnetization increase. 

Figure 5. Energy barrier (measured with pulsed magnetic field) vs bit area and free layer thickness. Bits ranged from 50nm to 90nm ellipses with aspect ratio from 2.3 to 3.5. Thicknesses varied from baseline (green circles) + (triangles)/- (squares) 10% in total moment.

Optimizing CoFeB-based perpendicular materials
Recent developments in CoFeB-based perpendicular materials [10, 11] have renewed interest in perpendicular MTJ devices. These devices are of great practical interest because MTJ stacks based on CoFeB alloys and MgO tunnel barriers have already proven to have the highest MR values and meet many requirements for manufacturability. In devices with perpendicular magnetization, the strong perpendicular anisotropy from the CoFeB/MgO interface is used to create the large perpendicular anisotropy needed for the perpendicular free layer.

Theory predicts that free layers with a perpendicular easy axis may have a lower achievable Jc and a lower IC for a given Eb. Experimental data has shown similar Jc values with both types, Jc≈3MA/cm2, for Eb≈50-70kbT.

Since the energy barrier is related to the perpendicular magnetic anisotropy rather than bit shape, it is possible to use circular bits for potentially smaller cell sizes. Better IC/Eb ratios have been demonstrated for perpendicular devices but, in many cases, with Eb values that seem to be limited to less than required. However, the rapid progress in perpendicular MTJ device properties over the past two years is continuing and providing evidence that IC can be further reduced and Eb can be increased in practical devices [12-15]. These recent reports describe CoFeB-based perpendicular MTJ devices with diameters between 20 nm and 70 nm having energy barriers enhanced by improved materials and patterning techniques.  

Another key requirement for ST-MRAM is high quality switching. f

igure 6 shows the results of optimizing CoFeB-based, in-plane free layer materials for low error rates.

The non-Gaussian behavior demonstrated by some of the un-optimized bits is an extrinsic mechanism that does not affect all bits.

For example, the non-normal increase in error rate on the right side of figure 6b is seen in some bits, usually in only one bias direction [16], and has been termed “ballooning.” Other bits seem to plateau at a certain error rate rather than continuing to decrease with increasing Vsw. Such effects are usually worse for shorter switching pulses, a behavior indicating magnetic defects in the free layer that create metastable magnetic states which interfere with switching. 

Figure 6: Write Error Rate (WER) out of 10,000 attempts for 9 bits, nominally 85nm x 240 nm, with write pulses of 25ns duration applied for (P-to-AP)(V<0) and AP-to-P (V>0) switching. The black line is a fit of the experimental data assuming a Gaussian distribution of WER. Each panel is a different free layer material

Optimized material dramatically reduces the occurrence of such switching and improves the intrinsic properties as seen by the well-behaved distributions and low bit-to-bit variation in figure 6c. The overall improvement in σVc shown in figure 7, and particularly the improvement for short write pulses in the tp<20 ns range, show clearly how improvements in the magnetic materials can improve the intrinsic switching behavior.

Figure 7: ST switching sigma (%) vs. pulse duration (ns) measured for a standard CoFeB based free layer (black circles) and an optimized CoFeB based free layer (blue squares). The data was taken on kb ST-MRAM arrays integrated with CMOS.

Recent progress in magnetic switching
In addition to developments in devices with perpendicular magnetization, described above, there are continuing advancements in ultra-thin magnetic films and devices that may find applications in future MRAM technology.  Two exciting examples are electric field control of interfacial anisotropy and the generation of spin currents with the spin Hall effect (SHE). For example, spin-torque switching of both in-plane and perpendicular free layers using the SHE has already been demonstrated by Liu, et al. [17] and a transition from in-plane to perpendicular anisotropy was demonstrated in CoFeB/oxide systems by Kita, et al. [18]

The rapid pace of discovery in the fields of spintronics and MTJ devices/materials bodes well for continued improvements in MRAM technology. One can easily imagine approaches that combine new ways of controlling magnetic states with high tunneling magnetoresistance and spin-torque transfer to extend device scaling to smaller dimensions, reduce the energy needed to write, and provide additional degrees of freedom for circuit architectures.

A 64-Mb DDR3 ST-MRAM circuit (see figure 8) and a companion 16-Mb test vehicle have been designed and fabricated using 90-nm CMOS technology. Four standard Cu layers and one Al RDL layer are used with the MTJ located between M3 and M4.

Packaged in a JEDEC standard DDR3 BGA, the 64-Mb DDR3 ST-MRAM is compatible with commercially available controllers. Supporting x4, x8, and x16 configurations, the 8-bank architecture minimizes initial latency while sustaining 1.6GT/s (DDR3-1600) sequential data rate.

Figure 8: Everspin 64-Mb DDR3 ST-MRAM Die Photo. Wordline drivers run vertically through the center of each of eight 8-Mb banks. Strips of column circuits run horizontally, dividing each bank into 8 sub-arrays.

With the optimized MTJ material described above, we have achieved full functionality of these 64-Mb devices, which apply new circuit techniques to address specific challenges of ST-MRAM. Switching distributions for 256 kb in our 16-Mb ST-MRAM test vehicle are shown in figure 9. A 100% natural switching yield is achieved for both antiparallel-to-parallel and parallel-to-antiparallel switching.

Figure 9: 256 kb switching distributions from our 16-Mb ST-MRAM test vehicle for both AP-to-P (blue) and P-to-AP (red) directions with applied switching voltage in arbitrary units. The write voltage pulse duration was 50 ns. The solid lines are error function fits to the data.

Figure 10 shows the operating region for up and down write bias using a March6N pattern run on the 64-Mb device, demonstrating a large write window with zero fails for a range of applied write voltages.

Figure 10: P-to-AP vs AP-to-P applied voltage shmoo plot for a March6N test pattern run on 16 Mb within the 64 Mb. Each square represents pass/fail, with green signifying zero fails and red signifying more than zero fails. The voltage step size is approximately 10 mV and the origin is offset from zero for both axes.

We have demonstrated high speed DDR3 functionality by achieving zero fails on 64-Mb devices with the March6N pattern at 1.5V VDD.

Full functionality of these parts was further demonstrated using an evaluation board controlled by an industry standard FPGA.

Our results demonstrate high-quality switching and high performance for integrated arrays of CoFeB/MgO-based MTJ devices with in-plane magnetization.

Initial results from a 64-Mb circuit showing fully functional DDR3 operation is an important step toward the first ST-MRAM product introduction.

Recent progress in perpendicular materials, SHE, and electric-field control of anisotropy show that there is great potential for continued improvement and scaling of MRAM technology.

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