http://www.eetimes.com/design/memory-design/4407727/Voltage-controlled-MRAM–Status–challenges–and-prospects?cid=Newsletter+-+MCUs+DesignLine
Voltage-controlled MRAM:
Status, challenges and prospects
Pedram Khalili and Kang Wang, University of California, Los Angeles
2/25/2013 5:24 PM EST
Magnetic random access memory (MRAM) using the spin-transfer torque (STT) effect has developed into a very active area of research and development over the past decade.
Years of research have been followed by increased interest from the industry in recent years.
The first 64-Mbit STT-MRAM product was announced by Everspin Technologies in late 2012, and several other companies are actively developing the technology and expected to follow with products in the near future.
STT-MRAM provides nonvolatile storage of information, high read and write speeds, lower energy dissipation compared to existing and emerging nonvolatile memories such as flash and resistive RAM (see figure 1), and very high endurance, making it a promising candidate as a nonvolatile RAM for both embedded and standalone applications.
Overall it provides orders of magnitude improvements over the currently dominant nonvolatile flash memories in every aspect except for density and, hence, cost per bit.
Figure 1: Comparison of speed and energy efficiency among existing (NAND and NOR flash) and emerging (MeRAM, STT-MRAM, phase-change, ferroelectric, and resistive RAM) nonvolatile memory technologies.
STT-MRAM: Switching current and retention time
One way of looking at the potential benefits of adopting MRAM is by reviewing the present memory hierarchy in terms of speed and density, ranging from slow, ultra-high-density memories used for storage such as hard disk drives and NAND flash, to ultrafast but very low-density memories such as SRAM (see figure 2).
STT-MRAM can potentially deliver an advantage in terms of this density/speed tradeoff, in addition to bringing nonvolatility to the lower right corner of the plot, which is currently occupied by volatile memories such as SRAM and DRAM.
Figure 2: STT-MRAM and MeRAM on the memory landscape. Reduction of switching current (and going from current-controlled to voltage-controlled memory devices) improves memory density and energy efficiency.
STT-MRAM typically uses a one transistor, one magnetic tunnel junction (MTJ) or 1T-1MTJ structure (see figure 3), in which a CMOS transistor is used as a select device and drives the write currents through the bit for writing of information.
Opposite bits of information are written using currents of opposite directions.
The bit itself consists of an MTJ, in which information is encoded as the relative orientation of a magnetic free layer with respect to a magnetic fixed, or pinned, layer.
At scaled technology nodes, the magnetization of both films will be perpendicular to the sample plane (up or down) to take advantage of the built-in magnetic anisotropy of the material, as opposed to using in-plane shape to define the stable bit directions, an approach that is not scalable.
Figure 3: Schematic representation of a 1T-1MTJ STT-MRAM/MeRAM cell
This current-controlled 1T-1MTJ structure implies that the density of STT-MRAM is defined by the size of its access transistor (rather than the size of the magnetic bit), which, in turn is proportional to the write current of the magnetic bit.
The lower the switching current Ic of the MTJ, the smaller the corresponding access transistor, and, hence, the larger the memory density. In addition, smaller switching currents also result in lower write energies for the STT-MRAM bits, thereby improving the energy efficiency of the memory.
Hence, reduction of the switching current Ic is an important driving force in STT-MRAM development for practical applications with low power and/or high density requirements.
Important performance attributes
In addition to the switching current, another important performance characteristic of MTJ bits is their retention time (i.e. nonvolatility), which is determined by the energy barrier Eb between the two magnetic states of the free layer. The larger the value of Eb, the more difficult it is for thermal fluctuations to overcome this barrier to induce false switching events; as a result, retention time increases.
Typical values of Eb for 10 years retention in a 1-Mbit array are approximately 60 kT, but the required Eb values may be larger depending on array size and operating conditions.
As mentioned before, large currents required to switch STT-MRAM bits require fairly large transistors to drive them, limiting the memory density.
This is in particular a problem for high-speed writing (less than 10 ns), since the switching current of STT-MRAM increases when the write pulse width is reduced.
Reduction of the switching current, however, has to be performed at a constant retention time, and hence the real device-level scalability criterion for STT-MRAM is to reduce the ratio Ic/Eb.
The smaller this ratio, the smaller the access transistor width can be made for a given technology node and retention time, hence improving the scalability of STT-MRAM. Interestingly, however, for STT-based switching of perpendicularly-magnetized MTJs, the ratio Ic/Eb is largely set by fundamental physical constants and material parameters with a limited tuning range (in particular by magnetic damping).
This means that scaling with a constant-Eb rule (i.e. keeping the retention time constant) requires switching currents to remain nearly constant across technology nodes for STT-MRAM. That is unfavorable in terms of scaling as it does not allow for a significant scaling of the transistor width.
The value of Ic/Eb, when combined with the current drive capability of transistors at a given technology node, determines the bit density and hence the application space and cost per bit of STT-MRAM. Current Ic/Eb values of approximately 0.5 µA/kT or higher impose access transistor sizes that are larger than the minimum size approximately at the 32-nm node and below (see figure 4), resulting in a penalty in terms of cell size and bit density.
Achieving scalability to below 10 nm, which enables DRAM-like cell sizes of approximately 6F2 at F less than 10 nm, is estimated to require a much smaller scaling parameter of Ic/Eb < 0.1 µA/kT for STT-MRAM.
This requires significant advancements in material engineering, especially in the magnetic free layer design.
In order to provide for an improved scaling scenario, as well as to reduce the energy dissipation associated with the current-induced write mechanism, one can use non-STT write mechanisms for magnetic memory bits that can replace or complement the STT-based approach used in today’s MTJs.
In the following we describe voltage-controlled (i.e. electric-field-controlled) magnetic tunnel junctions, or VMTJs as candidates for this type of beyond-STT magnetoelectric RAM (MeRAM) and present recent experimental results.
Figure 4: Effect of switching current (Ic/Eb ratio) on the scalability of access transistor size in STT-MRAM. Scaling is significantly improved by dramatic reduction of the switching current, such as through the adoption of a voltage-based write mechanism.
Voltage-controlled memory: MeRAM
Several approaches have been explored for the realization of electric-field-controlled magnetic (i.e. magnetoelectric) devices, including the use of single-phase multiferroic materials, multiferroic heterostructures in which magnetic and electrical properties are coupled through strain, and dilute magnetic semiconductors in which carrier-mediated ferromagnetism is controlled by a gate voltage.
A set of devices of particular practical interest for MeRAM are those that use the recently demonstrated voltage-controlled magnetic anisotropy (VCMA) effect.[1-4] These devices use metal/dielectric layered structures such as iron cobalt boron/magnesium oxide (FeCoB/MgO) thathave been commonly used in previous generations of MRAM, thereby maintaining manufacturability and transfer of existing know-how.
The free layer material has a magnetic anisotropy–a preferred magnetic axis–that can be modulated by voltage, hence allowing for voltage-induced switching of the magnetization.
VCMA structures also offer readout via the tunneling magnetoresistance (TMR) effect, thereby sharing an essential characteristic of other types of MRAM.
They offer an opportunity for fairly fast technological realization and commercial viability, given that they use materials and manufacturing processes very similar to those used in existing MRAM technologies such as STT-MRAM.
It has been demonstrated that the interface of dielectric oxides such as MgO with metallic ferromagnets such as FeCoB can be designed to exhibit a significant perpendicular magnetic anisotropy, which has been used to realize perpendicular magnetic tunnel junctions for STT-MRAM. Interestingly, this perpendicular magnetic anisotropy is also highly sensitive to electric fields at the interface; i.e., voltages applied across the dielectric oxide (see figure 5).
If MgO is used as the dielectric barrier, this effect can be incorporated into magnetic tunnel junctions with free and fixed magnetic layers, exhibiting TMR ratios of greater than 100%, which allow for readout of the voltage-induced changes of magnetization in the ferromagnetic free layer. Since the manipulation of the free layer magnetization in these devices is performed via voltage, rather than current, the MgO layer can be designed to be thick enough to reduce parasitic conductance through it. We therefore refer to such a device as a voltage-controlled magnetic tunnel junction, or VMTJ, to distinguish it from regular MTJs which primarily use the STT effect (although in principle, both effects can be combined to offer superior performance in the same device).
Figure 5: Schematic representation of voltage control of magnetic anisotropy at the interface of magnetic metals and dielectric layers (e.g. FeCoB-MgO). Electric fields modify the occupancies of different orbitals at the interface, resulting in a reorientation of magnetic moments.
The VCMA effect can be used to switch magnetic tunnel junctions. Switching is accomplished through the modification of perpendicular anisotropy when the voltage is applied. Different voltage pulse amplitudes of the same polarity will switch the device in opposite directions (i.e. write opposite bits of information into it), thereby allowing for bidirectional switching without the need for an external magnetic field.
This unipolar voltage-controlled behavior, as opposed to the bipolar STT behavior in which opposite current polarities are used to write opposite bits of information, is a distinguishing feature of VCMA-based magnetic memory bits.
The switching direction in this case is determined by the pulse amplitude rather than polarity, which is used in STT-MRAM. We refer to memory arrays based on such VCMA-based VMTJs as magnetoelectric random access memory, or MeRAM.
An example of the measured switching probability as a function of voltage pulse amplitude for a nanoscale MeRAM bit is shown in figure 6. The device has a resistance-area (RA) product greater than 10x larger than in typical STT-MRAM bits, limiting the amount of current flow during switching and ensuring a VCMA-based (non-STT) switching mechanism.[1] Note that the same polarity of voltage is used for switching in both directions. The device is thermally stable with Eb greater than 40 kT. Details of the device design and measurement data are presented in.
Figure 6: Photographs and microscope images of MeRAM devices developed at UCLA (top); and measured switching probability as a function of write voltage for a MeRAM bit (bottom). Note that switching is unipolar, i.e. different bits of information are written using voltages of the same polarity, but different amplitudes.
MeRAM: Scaling, challenges and prospects
In a fashion analogous to STT-MRAM, one can define the switching voltage Vc for a MeRAM device, with the associated scaling parameter Vc/Eb which should ideally be minimized.[2] Unlike STT-based devices, however, a constant-Eb scaling rule for VMTJs does not necessarily put a constraint on the size of the access transistors, since leakage currents during writing of MeRAM cells can be designed to be substantially smaller than in STT-MRAM. VCMA devices can thus potentially allow for minimum-sized transistors to be used down to much smaller technology nodes less than 10 nm, thereby providing a pathway for scaling of MRAM while maintaining high storage capacity and low cost per bit.
A similar scaling advantage is possible in terms of energy efficiency. While MeRAM already provides an advantage over STT-MRAM in terms of switching energy per bit by eliminating the need for large currents through the device, this advantage grows quickly as bit dimensions are scaled.
This is due to the fact that, assuming a constant write time across technology nodes, STT-MRAM bits retain an approximately constant write energy and write current if a constant retention time is required at scaled technology nodes.
This energy advantage is especially important in applications integrating memory and logic functions in the same circuit, where nonvolatile memory bits are expected to switch more frequently than in standalone memory, and hence need to be more energy-efficient.
Successful realization of these potential advantages will require additional development and innovations in the design of improved MeRAM bits.
In particular, it is important to maximize the VCMA effect (i.e. reduce Vc) through materials optimization, while maintaining high TMR for readout. A sufficient margin will have to be maintained between different write voltages (set/reset voltages in figure 6) and the breakdown voltage Vbd of the VMTJ devices.
This will require reducing the Vc/Eb ratio from the present approximately 30 mV/kT [1, 2] to less than 10 mV/kT to maintain compatibility with CMOS read/write circuitry and typical MgO breakdown voltages of approximately 1 V. It should be noted, however, that MeRAM can potentially also achieve improved performance in terms of breakdown voltage and reliability due to its increased dielectric barrier thickness compared to STT-MRAM.
In summary, voltage-controlled magnetic memory devices can provide a pathway toward achieving densities and energy efficiencies better than those available in current STT-MRAM memory cells.
While maintaining the same manufacturing processes and advantages of STT-MRAM such as nonvolatility, high speed and high endurance, MeRAM devices may complement or eventually replace STT to achieve improved memory capacities and lower cost per bit.
The realization of this paradigm will require materials innovations to develop bit structures with improved voltage control (lower switching voltage) while maintaining readout (TMR), nonvolatility, and control of breakdown voltage distributions to enable integration into large memory arrays.
References
[1] J. G. Alzate et al., "Voltage-Induced Switching of Nanoscale Magnetic Tunnel Junctions," Technical Digest of the IEEE International Electron Devices Meeting (IEDM 2012), San Francisco, CA, pp. 681-684, December 2012.
[2] P. Khalili Amiri, et al., “Electric-field-induced thermally assisted switching of monodomain magnetic bits,” Journal of Applied Physics 113[1], pp. 013912-013912-5 (2013).
[3] W.-G. Wang, et al., “Electric-field-assisted switching in magnetic tunnel junctions,” Nature Materials 11, pp. 64–68 (2012).
[4] Y. Shiota, et al., “Induction of coherent magnetization switching in a few atomic layers of FeCo using voltage pulses,” 11, pp. 39–43 (2012).
About the authors 
Pedram Khalili is a Research Associate with the Department of Electrical Engineering at the University of California, Los Angeles (UCLA).
At UCLA he has been project manager of several research programs on spintronic memory and logic since 2009, including the DARPA STT-RAM and Non-Volatile Logic programs.
He is also affiliated with the Western Institute of Nanoelectronics (WIN), and the NSF center on Translational Applications of Nanoscale Multiferroic Systems (TANMS). He has served as a Guest Editor for Spin, and has also served on the technical program committee of the Joint MMM-Intermag Conference. 
Kang L Wang is Raytheon Professor of Electrical Engineering at the University of California, Los Angeles (UCLA).
He is also director of the Western Institute of Nanoelectronics (WIN), and served as Director of the MARCO Focus Center on Functional Engineered Nano Architectonics (FENA) for ten years from 2003 to 2013.
He currently serves as the Editor-In-Chief for the IEEE Transactions on Nanotechnology, and is on the editorial board of the Encyclopedia of Nanoscience and Nanotechnology (American Scientific publishers). He also serves on the editorial boards of Spin, Handbook of Semiconductor Nanostructures and Nanodevices, as well as several other journals.
He is a Fellow of the IEEE, is a recipient of the Semiconductor Industry Association University Research Award, the IBM Faculty Award, the Semiconductor Research Corporation Technical Excellence Achievement Award, and the SRC Outstanding University Service Award.
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