FPGAs in the era of silicon convergence
Posted:03 Jan 2012
Semiconductor technology has entered a new period in its evolution.
The expectation is gone that every 18 months would bring a new process node with greater transistor density, greater speed and lower power.
Today at 28nm we see chips with the capacity to implement entire systems, save for the power components and commodity memory. But process engineers, circuit designers, chip designers and architects must all work together to find improvements in system performance and energy efficiency in an increasingly difficult technology.
This change is having profound effects all across the semiconductor industry, driving up engineering costs, increasing risks, and pushing customer-specific systems-on-chip (SoCs) beyond the reach of most systems developers. It is also changing the nature of FPGA companies and their relationships with their customers.
FPGAs are among the first designs to use and to stress-test a new process generation.
For example,Altera Corp. began shipping some of the powerful and complex members of its tailored 28nm FPGA family, built in TSMC’s highest-performance 28nm process, in early 2011. Doing this required an intimate relationship with our foundry, based on the accumulated experience of working together at ten earlier production nodes. Both parties had to cooperate in process engineering, transistor design and circuit design in order to achieve shippable yields on FPGAs that actually deliver the inherent benefits of the new process early in the process life.
But the demands of new technology nodes are beginning to reach beyond the level of circuit design, influencing design choices at the chip, and even the system level. For example, consider high-speed serial interfaces.
Today, Altera is shipping Stratix V FPGAs with highly-configurable 28Gbit/stransceivers, thanks to a combination of process, device and circuit innovations. But in today’s systems-directed world, the industry’s fastest integrated transceivers themselves are just the beginning of the story. Serial links require controllers fast enough to keep up with the transceivers.
The controllers require on-chip busses fast enough, and buffers large and fast enough, to support them.
And all of these blocks must meet energy-consumption requirements that depend on the particular system, its application, and its use models.
Accordingly, Altera’s transceiver technology must offer choices. Some of these choices are at the circuit level—different versions of the transceivers have been designed to operate at different speeds and with different levels of energy consumption. By selecting a chip from the tailored 28nm family, a system design team can match transceiver speed and energy-consumption to their specific system requirements.
Other decisions are at the block level. Should performance-critical and energy-hungry controllers such as PCI Express Gen3 or DDR3 be implemented in programmable cells, or in fixed hardware? Should such blocks connect into the programmable fabric, or to a hard-wired system bus, or both? The answers depend on the application.
High-speed serial is not the only example. Many system designs today include both an FPGA and one or more 32bit embedded processors. Should architects purchase their CPUs as application-specific standard-product ICs or advanced microcontrollers, or might they implement the CPUs in an FPGA?
If the latter, should they use a soft core in the programmable fabric, or select an FPGA—such as Altera’s SoC FPGAs—with hard ARM processors?
And how will architects partition their designs so that the highest-bandwidth traffic, such as that between caches, DRAM controllers, and accelerators, does not cross chip boundaries? Once again the answers depend on the application.
There is no one solution for every customer, no matter how convenient that might have been for the FPGA vendor.
Altera could not properly serve customers with just several different sizes and pin-outs of one chip design from one process. In order to fit the requirements of different applications, a family of FPGAs must offer choices in transceiver design; interface controller implementation; the size, speed, and power consumption of internal memory blocks; internal bus structures; CPU implementations; and many other factors.
Yet most system designs cannot bear the cost of an ASIC: one chip design still has to serve many customers. The only way to resolve this dilemma has been for Altera to learn in detail about our customers’ system designs and find areas of commonality that optimize both the fit to application needs and the size of served market. It is a delicate, knowledge-intensive process that draws us much closer to our customers’ design teams.
This intimate relationship with Altera’s key customers—design teams who have both deep application expertise and long-standing familiarity with FPGAs, has been developing for years. But today a second dimension is opening out in our engagement with customers: the realm of application-specific solutions.
In 2012, many of the most competitive system design teams have become highly specialized. They are experts at creating competitive advantages for their products, but they rely on their silicon vendors to provide a system platform on which they can build. Such design teams may need full sets of application-specific intellectual-property (IP) cores and an automated IP-assembly tool such as Altera’s Qsys. Or they may require complete reference designs. As design teams continue to specialize, the responsibility for providing the bulk of the system design is shifting toward their silicon partners.
This, then, is the changing face of Altera’s world in 2012. We continue, at 28nm and beyond, to seek process, device, and circuit innovations with our foundry partner, ensuring continued technology leadership at the silicon and circuit level. At the same time we work intimately with our customers to ensure we deliver products tailored closely to their specific power, performance, and cost requirements. And we continue to build on our base of applications understanding in order to deliver IP and reference designs that our customers can exploit to accelerate their design schedules. All this is necessary if Altera’s leadership is to enable our customers’ leadership.
– John Daane
President and CEO