NXP boosts in-vehicle networking with 48V transceivers

三月 23, 2012
By


NXP boosts in-vehicle networking with 48V transceivers

Posted:23 Mar 2012

http://www.eetasia.com/ART_8800663721_499495_NP_27832be5.HTM?8800092101&8800663721&click_from=8800092101,8723946550,2012-03-23,EEOL,ARTICLE_ALERT#

NXP Semiconductors N.V. has unveiled a portfolio of FlexRay transceivers that supports the automotive industry move toward a 48V board net in future vehicles.

The 48V FlexRay products claim to be the industry’s first that are capable of supporting the new board net by offering up to ±60V robustness.

According to NXP, the devices deliver reduced CO2 emissions due to very low current consumption in standby and sleep mode plus high immunity to ESD.

While other companies continue to design using lower voltage CMOS processes, NXP’s ABCD3/9 technology offers high voltage features far beyond 60V at a high density of digital logic, boasted NXP.

The family of FlexRay transceivers includes the TJA1081B that will be available by 2Q12.

The device is EPL V3.0.1 and JASPAR compliant and touts gap-free undervoltage specification.

It features improved EMC and is compliant to OEM specifications.

Likewise, it offers Sleep-function (VBAT supplied, incl. voltage regulator control).

Other members of the family to be released in the year are the FlexRay and the TJA1085.

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東京大學開發的量子點型太陽能電池，100倍聚光時電池單元轉換效率超過20％

三月 23, 2012
By

東京大學開發的量子點型太陽能電池，100倍聚光時電池單元轉換效率超過20％

http://big5.nikkeibp.com.cn/news/econ/60340-20120320.html

東京大學尖端科學技術研究中心教授岡田至崇

開發的中間帶方式的量子點型太陽能電池單元

在100倍聚光時的電池單元轉換效率達到了20.3％。

該成果是與馬德里理工大學共同研究而獲得的，

詳細內容將在2012年4月16～18日于西班牙托萊多舉行的國際學會

「CPV-8（8th International Conference on Concentrating Photovoltaic Systems）」上發表（學會網站）。

　　中間帶方式的量子點型太陽能電池只單純注入量子點還不夠，還必須要保證中間帶能夠發揮作用。

以前岡田教授在中間帶方式的量子點型太陽能電池的多項研究中，

已經證實了室溫下經由中間帶的兩個能級的光吸收可增加電流。

　　此次為了對已經證實中間帶能夠發揮作用的電池單元用於聚光系統時的特性進行測評，

岡田教授與擁有聚光系統評測設施的馬德里理工大學展開了共同研究。

　　共同研究獲得了以下成果：

100倍聚光時電池轉換效率達到20.3％，1000倍聚光時電池轉換效率達到21.2％。

今後將增大量子點的密度，同時對層構造進行降低串聯電阻的改進，

使電池單元能承受聚光產生的大電流，還將改進電極構造，

力爭在100倍聚光時實現35％的電池單元轉換效率，

在1000倍聚光時實現45％的電池單元轉換效率。

（記者：河合 基伸，《日經電子》）

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Xilinx, Micron demo FPGA, RLDRAM 3 memory interoperability

三月 23, 2012
By

Xilinx, Micron demo FPGA, RLDRAM 3 memory interoperability

Posted:16 Mar 2012

http://www.eetasia.com/ART_8800663232_499485_NP_2c2b5a2b.HTM?8800091821&8800663232&click_from=8800091821,8723946550,2012-03-16,EEOL,ARTICLE_ALERT#

Xilinx Inc. and Micron Technology Inc. have demonstrated the first t public hardware FPGA interfacing with RLDRAM 3 memory. RLDRAM 3 is a new and emerging memory standard for high-end networking applications such as packet buffering and inspection, linked lists, and lookup tables. It enables 40G and 100G networking systems that require higher speed, higher density, lower power and lower latency.

Operating with Virtex-7 and Kintex-7 FPGAs at data rates up to 1,600Mb/s, Micron’s RLDRAM 3 memory combines high density, high bandwidth and fast SRAM-like random access to enable a 60 percent higher data rate and memory bandwidth compared to previous generation (Virtex-6 FPGAs/RLDRAM2 memory standard) memories, the companies said.

Virtex-7 and Kintex-7 FPGAs are designed with the necessary IO standards and architectural components for optimal interfacing with RLDRAM 3, providing a significant boost to system performance for high-performance wireless and wired networking systems. RLDRAM 3 memory uses innovative circuit design to minimize the time between the beginning of an access cycle and the instant that the first data is available. Ultra-low bus turnaround time enables higher sustainable bandwidth with near-term balanced read-to-write ratios.

"The new RLDRAM 3 interface is ideal for Xilinx and Micron’s mutual customers in the high-end networking space who require higher speed, higher density, lower power and lower latency," said Derek Curd, technical marketing manager at Xilinx. "The RLDRAM 3 hardware demonstration shows how we’re able to achieve a much more efficient transfer of network data."

Hardware demonstrations of the Xilinx RLDRAM 3 Memory interface IP core are available now with user configurable IP cores available in ISE Design Suite 13.4 in September 2012.

Qualified Micron RLDRAM 3 memory devices are currently available in x18 and x36 organizations across all speed grades from 800 to 1,066MHz.

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Are you ready for OMAP 5?

三月 23, 2012
By

Are you ready for OMAP 5?

http://www.eetasia.com/ART_8800663237_499489_NP_19bc8746.HTM?8800091821&8800663237&click_from=8800091821,8723946550,2012-03-16,EEOL,ARTICLE_ALERT

Posted:16 Mar 2012

Texas Instruments Inc. is putting its highly anticipated OMAP 5 platform on center stage.

The OMAP 5 will be the newest from TI‘s OMAP processor family that will target smartphones and numerous other markets—from automotive to the http://www.eetasia.com/ART_8800663237_499489_NP_19bc8746.HTM?8800091821&8800663237&click_from=8800091821,8723946550,2012-03-16,EEOL,ARTICLE_ALERT.

According to TI, the platform uniquely enables leading digital hubs to deliver premium content while consumers capture, edit, store, and share their own content across numerous end equipment.

The result is a multimedia-rich, multitasking-intense visual experience without compromise, the company said.

The OMAP platform has long harnessed a balanced system identified as the smart multicore architecture to deliver the highest applications processing performance at the lowest possible power, TI explained.

The evolution of this architecture, that today comprises the OMAP 5 platform, changes what’s possible in mobile computing, and delivers a superior user experience leveraging TI’s mobile-optimized 28nm process, the company added.

Mobile applications benefit from the distribution of interdependent activities across multipleprocessors to create fluid performance and fast responsiveness.

However, in reality most of these applications today are single-threaded or have a dominant single-threaded task or process, and are thereby unable to partition across large numbers of CPU cores within a platform.

Thus, the OMAP5430 processor includes two ARM Cortex-A15 cores that provide the highest single-thread performance of any ARM CPU.

Unique to the OMAP 5 smart multicore architecture is the use of two ARM Cortex-M4 cores to complement the two ARM Cortex-A15 cores.

The M-class cores are appropriately assigned real-time control processing of multimedia tasks, like video encoding and decoding, freeing the main CPU cores to manage high level operating system tasks.

In addition to minimizing the Cortex-A15 cores’ interrupt rate, this off-loading function delivers an invaluable power savings—as much as 10 percent of the system power when encoding and decoding high definition H.264 content, for example.

In a market driven largely by graphics performance, the ability to raise the bar without increasing power consumption is a competitive advantage benefitting any application’s performance.

TI boasts that the OMAP 5 platform represents several upgrades to preceding OMAP processor families, including the introduction of a second GPU.

Through the use of dual-core PowerVR SGX544 GPUs from Imagination Technologies, the OMAP5430 processor outperforms the competition by up to 4x across common industry graphics benchmarks, TI said. Imagination Technologies differentiates its SGX544 cores through the use of a tile-based deferred rendering architecture, which reduces bandwidth usage and minimizes power consumption when compared to competitive solutions.

TI harnesses this graphics performance by complementing the GPUs with unique OMAP platform capabilities, while running the cores at their maximum limit of 532Mhz.

TI further explained that the SGX544 cores are augmented by still another unique OMAP architecture feature, a dedicated 2D hardware-accelerated composition engine that can support up to 8 layers of high resolution composition without the need to go to external memory.

The smart multicore system off-loads compositing to the composition engine, lowering power consumption by as much as 10x what the GPU would expend running the same eight layer composition process, the company noted.

This is done without passing data back to the memory, freeing the memory bandwidth for other multitasking functions.

OMAP 5

The OMAP 5 claims to be the only applications processing platform that can deliver unprecedented performance inside of a sub-two-watt power envelope to meet device and application requirements.

Mobile platforms are constrained to a fixed thermal budget—otherwise a device might feel too hot in a user’s hand. If the processor exceeds this budget, it must be throttled. This is a process that can limit the real performance of the device. Navigating this challenge to yield the ultimate performance within the mobile thermal budget, the OMAP 5 platform balances the right performance to deliver under this thermal constraint the highest possible effective MIPS, reaching upwards of 35 percent greater than the latest quad-core market solutions. Under a realistic thermal budget representing the constraints of a hand-held device, the OMAP smart multicore architecture, coupled with TI’s 28nm process, delivers performance unachievable by other processors—whether they leverage the same or different numbers and types of CPUs.

As today’s users expect DSLR-like performance from their mobile devices.

The OMAP 5 platform’s image signal processor delivers lighting fast capture of 16MP in 0.5s, 24MP at 30fps with zero shutter lag, and enhanced low-light performance.

It also enables a device to use four simultaneous camera sensors for new end user applications.

For example, users operating OMAP 5 processor-driven devices are also able to capture 1080p 60fps video while simultaneously taking 12MP still images. TI’s advanced camera APIs will also support new features like night shot, advanced HDR and digital re-focusing, which allows users to focus an image even after the picture is taken.

"We have achieved a superior design in the OMAP 5 platform, setting it in a class all its own," said Remi El-Ouazzane, vice president and general manager, OMAP platform business unit, TI. "The market requires unprecedented performance inside of a sub-two-watt power envelope to meet device and application requirements.

The OMAP 5 platform is the industry’s only applications processing platform capable of delivering on that need—creating the ultimate, most exciting end user experience possible in the market’s current timeframe while setting the stage for what’s to come," El-Ouazzane added.

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瑞薩電子宣佈針對單馬達與變頻器控制用途，推出全新32位元RX63T MCU

三月 23, 2012
By

瑞薩電子宣佈針對單馬達與變頻器控制用途，推出全新32位元RX63T MCU

為價格敏感的工業與家電市場提供更強的計時器與類比功能

瑞薩電子RX63T 32位元 MCU

瑞薩電子RX63T 32位元 MCU

TOKYO, Japan, February 28, 2012 — 先進半導體解決方案之頂尖供應商瑞薩電子(TSE：6723)宣佈推出RX微控制器（MCU）系列的最新產品－RX63T。RX平台是以新一代的RX CPU為基礎，並整合了瑞薩電子現有的16位元與32位元MCU產品功能。

全新的RX63T系列共有六項產品，除了高速、高效能、低功率的32位元RX600系列之外，新的RX63T系列更採用特殊的變頻器控制計時器與類比功能，滿足當今變頻器控制用途之需求。

全新RX63T系列為RX62T系列的延伸，以更小的針腳封裝、精簡的記憶體規格與加強的安全功能，達成瑞薩電子進一步降低成本的承諾。

全新的MCU除了可節省系統成本外，更可減少空調、洗碗機、太陽能變頻解決方案、照明控制與PFC的耗電量。

RX63T MCU包含兩個三相位馬達控制計時器電路：

即「多功能計時電路集（MTU3）」與「16位元的通用型PWM計時器（GPT）」。

這兩款計時器皆針對支援低系統成本的高效驅動器所設計，MTU3支援額外的PWM。

GPT則可獨立控制單相位變頻器的四組通道，其中前後緣的延遲時間（dead-time）也可分別控制。.

計時器使用與CPU於80 MHz時相同的時脈，可以12.5奈秒（ns）的解析度，提供更廣的PWM輸出波形寬度控制。

全新RX63T系列的類比功能經過改良後，可進一步減少系統成本並支援馬達向量控制用途的簡易開發。

RX63T系列使用一個12位元的A/D轉換器，能在1 s的最低轉換時間內擷取類比輸入數值。

此外，A/D轉換電路可對三個輸入通道同時進行取樣的情況，12位元的A/D轉換器能輕易地應用於無感應器的向量控制法則，例如three-shunt或single-shunt電流偵測。

安裝於12位元A/D模組的雙資料暫存器，則用於支援連續A/D轉換。每一個比較器都有三種偵測等級，可輕易監控並緊急關閉外部IGBT。

RX63T系列MCU也結合許多安全功能，

例如搭載專用晶片時脈來源（IWDT）的獨立看門狗程式、

自動檢查功能、

可使RAM不需透過CPU進行檢查的DOC（資料運算電路）、

用於檢查時脈頻率的CAC（時脈頻率準確度測量電路），

以及可防止重要暫存器不慎遭到覆寫的RWP（暫存器寫入保護）等。

由於在向量控制演算法中常需要進行計算，因此RX63T也設有精準的浮點運算器（FPU），可簡化小數點的計算，提高整體處理效能。

RX63T系列裝置提供可擴充的記憶體解決方案，從32K快閃記憶體到最多搭載8KB嵌入式SRAM的64KB快閃記憶體，同時另外更提供8 KB資料快閃記憶體，能以背景操作（BGO）功能在程式執行時寫入資料。

內建的快閃記憶體是採用瑞薩電子經過市場好評的MONOS（金屬氧化氮氧化矽）科技，

能在不需要額外等候狀態（wait state insertion）的情況下，以100 MHz的速度進行存取，

進而在任何CPU頻率上發揮最高達1.65DMIPS/MHz的效能等級，

而且沒有任何快閃記憶體科技限制；

這些產品將提供48-pin與64-pin LQFP封裝版本。

為協助客戶縮短新的嵌入式系統開發週期，瑞薩電子、協力廠商與結盟合作夥伴皆提供各種軟硬體工具支援RX。

RX600系列搭載JTAG除錯介面，可讓客戶連接瑞薩電子E1或E20晶片除錯器或存取類似的JTAG協力廠商系統，

例如：J-Link（製造商：Segger）。

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World’s first optical FPGA technology demo from Altera

三月 12, 2012
By

World’s first optical FPGA technology demo from Altera

Clive Maxfield   3/6/2012 6:47 PM EST

http://eetimes.com/electronics-products/electronic-product-reviews/fpga-pld-products/4237631/World-s-first-optical-FPGA-technology-demo-from-Altera?Ecosystem=automotive-design

Changing how bandwidth-intensive applications can be designed and built, the folks at Altera have announced the world’s first demonstration of the company’s Optical FPGA technology.
Developed in conjunction with Avago Technologies, the demonstration shows how Altera’s optically interconnected programmable devices can significantly increase interconnect bandwidth while reducing overall system complexity, power, and price. The technology demonstration is one in a series of recent innovations delivered by Altera, including the industry’s first OpenCL program for FPGAs and 28-Gbps transceiver technology delivering the industry’s highest data rates with superior signal integrity. Altera has been showing select customers the demonstration over the last quarter and will showcase it at the Optical Fibre Communication Conference and Exposition (OFC) being held at the Los Angeles Convention Center from March 6 to 8, 2012, in booth 2825.
As data rates approach 100-Gbps and beyond, significantly more bandwidth is required for next-generation applications in the computer and storage, communication infrastructure, and broadcast markets. By integrating programmable devices and optical transceivers within a single package, Altera’s Optical FPGA technology can break through the reach, power, port density, cost, and circuit board complexity limitations of copper-based and conventional optical solutions.
"The Optical FPGA technology demonstration underscores Altera’s commitment to develop innovations that address major industry challenges and ultimately, enable new innovations," said Bradley Howe, vice president of IC Engineering at Altera. "As data rate demands continue to rapidly increase, engineers need to look beyond copper and traditional optical solutions in order to meet the performance, cost, and power demands of next-generation video, cloud computing, and 3D gaming applications."

The demonstration shows Altera’s Optical FPGA technology on a test board derived from the company’s Stratix IV FPGA 100G development kit, integrated with Avago Technologies’ 12-Channel MicroPOD optical modules. By integrating high-speed optical transceivers onto the package that holds the FPGA, the electrical signal path from the I/O pad of the chip to the input of the optical transceiver has been reduced to a fraction of an inch. This shorter path reduces signal degradation and jitter, improving signal integrity and reducing data errors caused by parasitic elements in the signal path. Such integration can also help engineers reduce their overall board development and engineering costs.

In a loopback configuration, the demonstration shows 100GbE traffic of assorted packet sizes sent and received using the chip’s internal traffic generator. The data path is sent back and forth through the FPGA transceivers and optical modules to achieve a bit error rate (BER) of 10^-12 or less. The short routing distance keeps signal integrity high and the emitted electromagnetic interference very low. Digital diagnostics monitoring (DDM), such as module case temperature and laser bias current, is also shown detecting potential issues and preventing link loss. This is especially critical for data center applications where link downtimes can equate to millions of dollars in lost revenue. Finally, the demonstration shows the optical FPGA’s unique heat-sinking capability, which ensures the optics stay within the standard 0°C to 70°C temperature range.
"As the world leader in Data Center optics, Avago worked with Altera to combine our proven MicroPOD optical modules with their Stratix FPGAs, taking the concept of embedded parallel optics to the next level of integration," said Philip Gadd, vice president and general manager of the Fiber Optics Product Division at Avago. "This will allow FPGA users to utilize the high bandwidth and compact size advantages of parallel optical interfaces that are currently used in data centers."
Click Here for more information on Altera’s optical developments,including an upcoming video and white paper.

蘋果推出新一代高解像度iPad

三月 10, 2012
By

蘋果推出新一代高解像度iPad

更新時間 2012年3月7日, 格林尼治標準時間19:59
http://www.bbc.co.uk/zhongwen/trad/science/2012/03/120307_apple_new_ipad.shtml
 

蘋果電腦公司星期三（7日）推出新一代高解像度iPad。

新款iPad最引人注意的是Retina屏幕，分辨率為2048×1536，是上一代產品的4倍

新iPad將於3月16日上市銷售，

首批上市包括美國、加拿大、英國、法國、德國、瑞士、日本、香港、新加坡以及澳大利亞。

不清楚新iPad在其生產地中國大陸何時上市。

從硬件配備看，新款iPad攝像頭有重大改進，前置攝像頭像素達310萬，後置攝像頭像素則達500萬。

用戶可以拍攝1080p的高清視頻短片。

新款iPad搭載A5X處理器。蘋果表示，A5X處理器速度是英偉達Tegra3的兩倍，性能是後者4倍。

新iPad還提高了網絡速度，支持4G LTE網絡，包括HSPA+以及HSDPA兩種技術標準。

外觀上，新款iPad厚9.4毫米，重量為635克。電池續航時間10個小時，但4G網絡狀態下，續航時間為9小時。

蘋果本次推出的iPad分為WIFI版本與4G版本。

雖然硬件配置大幅提高，但售價仍然與iPad2一致。

在新產品發佈會上，蘋果公司還推出蘋果手機和平板電腦運行系統iOS的升級版5.1。

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新iPad革命觸感 看得到摸得著

三月 8, 2012
By

新iPad革命觸感 看得到摸得著

http://www.libertytimes.com.tw/2012/new/mar/8/today-life15.htm

Apple今天凌晨2點發表新一代iPad，在截稿前掌握的消息，

包括名稱改成iPad HD，使用A5X處理器，加強圖形處理能力；

螢幕仍為9.7 吋，採用 Retina螢幕，解析度是2048×1536，

相機提升到500萬畫素，使用新版本的iOS 5.1。

iPad HD也將推出支援4G LTE網路的版本，

配合美國已經建置4G LTE網路的電信商，

但仍保留3G/Wi-Fi與Wi-Fi版本；

至於iPad HD儲存容量，最高達128GB。

蘋果也推出新的Apple TV網路電視機上盒，

支援iPad HD的Full HD無線播放（AirPlay）功能。

據傳，

蘋果將採用由芬蘭研發的革命性觸感回饋技術 Senseg ，

讓每個像素都能產生電脈衝，

形成觸覺回饋，因此不同材質將產生不同觸摸感受的「所見即所觸」，

像是螢幕上秀出石頭，手指像是可以摸到石頭，

此外，因為螢幕很耗電，電池容量加大。

（記者陳炳宏）

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Intel rolls first processor optimized for datacenters

三月 8, 2012
By

Intel rolls first processor optimized for datacenters

R. Colin Johnson  3/6/2012 12:01 PM EST

http://eetimes.com/electronics-news/4237522/-Intel-rolls-first-processor-optimized-for-datacenters

Intel announced its first processor optimized for the datacenter with 70 percent boost in performance for same energy consumed by up to eight-core processor per socket.

PORTLAND, Ore.—Intel Corp. says it has designed its first processor built from the ground up for the "green" datacenters of the future, claiming a 70 percent increase in performance for the same energy consumption.

The new E5-2600 also features a high-speed bi-directional ring encircling its up to eight cores per socket connecting up to 20 Mbytes of cache, quad DDR3 memory controllers and 40-lanes of PCI-Express 3 for input/output (I/O).
"The E5 is our first CPU optimized for the energy-efficient datacenter of 2015," said Jeff Gilbert, Sandy Bridge architect.

"It features twin 32-byte wide ultra-high-speed rings going in opposite directions to encircle the eight [Sandy Bridge] cores and connect them to cache."

The E5 family is also Intel’s first server processor family with integrated input/output (I/O), rather than using a separate chip, thereby reducing latency by 30 percent while doubling the bandwidth with PCIe3.

The E5 is also the first Intel server processor to support LAN-on-motherboard (LOM) by virtue of industry’s first integrated 10-Gbit per second Ethernet local-area network (LAN).

Intel also claims the E5 is its first processor optimized for a lowest idle power of 10-20 percent utilization.

A sophisticated power management agent puts separate power limits on the whole device, its cores, memory and I/O, then smartly manages them for optimal performance, energy efficiency or other datacenter goals.

Using dynamic switching, depending on load conditions and turbo requests, the E5 will automatically switch between "performance" and "low-power" modes plus a new "balance" mode that compensates for turbo requests by adjusting the voltage/frequency of other cores.

For instance, if datacenter managers decide to clamp power at a certain overall level, then the balance mode will adjust some cores down in voltage and frequency to compensate for the heavy load on a turbo-mode core.

The new turbo 2.0 mode is also smarter on the E5, employing better thermal management algorithms that keep track of how long a core has been held idle building up "turbo credits" that can be used when over-clocking is invoked.

Besides voltage and frequency scaling for each core, the new power management agent also manages energy efficiency in I/O by dynamically reducing its width in response to workload and thermal management goals.

Core power can be scaled from 50-to-95 watts, which likewise scales memory latency from 118-to-64 nanoseconds, while a "unicore" technique scales cache and ring frequency to match.

In all, 23 different parameters are adjusted by the E5′s running-average-power-limit architecture.

As a result of optimizations enabled by Intel’s Node- and Datacenter-Manager software, Intel estimates that up to 40 percent more servers can be installed per rack using E5 processors.


Intel’s E5-2600 processors will be available with up to eight cores encircled by a high-speed bi-directional ring connecting caches, memory, direct I/O.

Mixed-Signal Precision32™ 32-Bit Microcontrollers

三月 3, 2012
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Mixed-Signal Precision32™ 32-Bit Microcontrollers

http://www.silabs.com/products/mcu/Pages/32-bit-microcontrollers.aspx

Silicon Labs’ Precision32™ 32-bit microcontroller family is engineered to make your job easier. The Precision32 MCUs provide a highly integrated and flexible architecture, a rich peripheral set and low power consumption.

To ease development, Silicon Labs offers an Eclipse-based development suite including a full compiler, debugger and AppBuilder rapid prototyping utility at no charge.

Based on the ARM® Cortex™-M3 core, the new Precision32 SiM3U1xx and SiM3C1xx MCUs include USB and non-USB devices with 32–256 kB Flash, 8–32 kB RAM and 40–92 pin packages.




Patented Crossbar Architecture

Enables maximum system design flexibility & reduces board complexity and cost

32-bit Development Tools

Modular hardware system with everything needed to evaluate and develop code

Free Software Tools

Eclipse-based IDE with full compiler, debugger & AppBuilder rapid prototyping tool

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Unified Development Platform (UDP)

Silicon Labs offers an innovative, new approach in hardware support with the Unified Development Platform (UDP), featuring a unified mother board, modular boards, integrated LCD and ample real estate for prototyping, expansion and integration.

The UDP platform supports all of the following:

  • MCU code and firmware development (IDE, Configuration Wizard, example codes etc.)
  • RF design and optimization (WDS support, automatic board detection and firmware download, sample RF code, run-time PHY interface etc.)
  • Networks and protocol stacks (such as the wireless M-Bus stack)

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