AMCC

Asymmetric multiprocessing boosts subsystem isolation

四月 10, 2011
By

Asymmetric multiprocessing boosts subsystem isolation

Colin Holland

3/31/2011 2:34 PM EDT

The Diamondback APM86392 and APM86391 are the latest additions to the Applied Micro Circuits Corp.

PacketPro family of multi-core embedded processing devices.

The devices use asymmetric multiprocessing (AMP) to enable two or more independent subsystems to operate concurrently with effective isolation on a single chip.

This can improve application performance and reliability and is also designed to provide an easier migration to multicore designs with  flexibility for a range of embedded applications in networking, storage, printing, imaging, and multimedia access systems.

Many multi-core processors force software engineers to dedicate one of the cores as a master to control the operations of the other slave cores.

The PacketPro family uses AppliedMicro’s Scalable Lightweight Intelligent Management processor (SLIMpro) subsystem, to implement AMP on APM8639x processors without dedicating one of the cores as a master.

This enables completely separate and isolated partitions on a single chip, each with independent operating systems, applications, software, processing bandwidth, I/O and cache. Each subsystem is decoupled from other subsystems during software updates, crashes, rebooting, peak performance demands or other events that can interrupt continuous operations.
In the traditional master-slave design a system fail can require a complete reboot. Both subsystems would have to be taken down

to reboot one operating system due to dependencies from shared cache memory and other resources.The PacketPro technology allows the decoupling of cores without interruption or impact of other subsystems running on the same embedded SoC device only one core has to be restarted.  So each processor has separate and virtualized access to processor resources so that one subsystem can continue operation even if any of the other ones becomes inoperative.

The AMP approach is designed to aid developers who are migrating from single-core to multi-core designs by allowing consolidation of several applications onto one SoC without the re-engineering that typically accompanies porting of software to a multi-core environment.

This reduces overall development time and costs.

The SLIMpro subsystem also manages multiple power islands on the SoC to meet low-power, energy efficiency requirements.
The non-blocking architecture of PacketPro is arbitrated by queue management and traffic management so that each individual application should not suffer from a lack of processing resources

AppliedMicro’s Diamondback APM86391 single core devices and APM86292 dual-core processors feature PowerPC 465 processing cores operating at up to 1.0GHz with floating point units, 32 KB I- and 32KB D-cache, 256 KB L2 cache per processor, 32-bit DDR at 1066 Mbps DDR3 memory controller with optional ECC.


APM86292 dual-core processor

High-speed interfaces consist of GE ports with in-line classification, security and TCP/IP offload, three single lane PCI-e Gen 2, two USB 2.0 host with integrated PHYs, one USB 2.0 OTG with integrated PHY, and one SATA 2.0 ports.

The Serengeti evaluation platform is available now running up to 1.0GHz and exposes all interfaces available on the SoC. The PacketPro family is supported by an ecosystem of third-party suppliers such as WindRiver, VxWorks, Free BSD, Enea, NetBSD and others.

Samples quantities of AppliedMicro’s APM8639x SoCs are available now with production quantities expected later this year.

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Amcc multicore PowerPC

十月 14, 2010
By

 

Amcc multicore

http://www.appliedmicro.com/products/process.html

amcc multicore

AppliedMicro PacketPro™ Multicore Processor Family Provides Intelligent SoC Management for Embedded Applications

Second-generation platform unleashes breakthrough performance and flexibility in security, power management, high availability, core independence and concurrency

SUNNYVALE, Calif.–(BUSINESS WIRE)– Applied Micro Circuits Corporation (NASDAQ:AMCC), or AppliedMicro, today announced its next-generation PacketPro™ multicore processor System-on-a-Chip (SoC) family, designed with advanced subsystem and offload acceleration hardware to enable new levels of security, high availability, low latency, and power management for embedded applications.

AppliedMicro’s PacketPro family of multicore embedded processor SoCs provide intelligent management of multiple functions. (Photo: Business Wire)

PacketPro is AppliedMicro’s second-generation embedded processor SoC family and the first to feature offload of critical features for multiple PowerPC® processors with frequency capabilities ranging in performance from 600 MHz to 2.0 GHz and beyond. The innovative SoC subsystem design features the Scalable Lightweight Intelligent Management processor or SLIMpro™ to enable breakthrough flexibility in SoC power management, protected asymmetric multiprocessing (PMP), failover protection, resiliency and end-to-end security for a wide range of mission-critical applications in wireless and wired networking, multi-function printer, industrial, access point markets.

Each device introduced into the PacketPro family enables multiple, concurrent operating systems (OS) while providing resource protection (processors, memory and I/O) that each domain operates in a transparent, independent and protected mode. It also enables application-aware and usage-based power management to reduce energy consumption. The multi-level crypto engine offers simultaneous wire-speed performance along with investment protection against product cloning and hardware-software tampering.

“PacketPro is an advanced SoC architecture that offers an ideal combination of high-performance and low power consumption at low cost,” said Vinay Ravuri, Vice President and General Manager of AppliedMicro’s Processing Products Division. “Flexible power management enables deep sleep operating power of less than 200mW and includes Wake on LAN, USB, PCIe and others. With the ability to scale-down and turn off SoC resources when not in use and to scale-up to full power when system demands require, PacketPro provides developers unprecedented ability to dynamically control power consumption levels.”

AppliedMicro developed the PacketPro multicore SoC architecture specifically in response to developers’ need to manage abundant on-chip resources as the industry shifts from single core to multicore applications. These enhanced management capabilities help developers address the ongoing explosion in bandwidth, the growth of converged network applications and green energy initiatives. PacketPro also features configurable offload engines for in-line packet processing, security, traffic classification, shaping and queue management to relieve the main processor complex.

"Simply adding more cores to a chip doesn’t necessarily solve the customer’s problem," said Linley Gwennap, principal analyst of The Linley Group. "AppliedMicro’s PacketPro is a well thought-out SoC architecture that addresses critical system-design issues such as end-to-end security, high availability, and flexible power management. The non-blocking multi-hub queuing fabric delivers a deterministic low-latency solution for packet processing."

The AppliedMicro PacketPro family features performance of up to 2 GHz per core, 32KB L1 I/D & 256KB dedicated L2 cache per core, support for full symmetric multiprocessing (SMP) and ultra flexible asymmetric multiprocessing (AMP). Memory and bus architecture supports 16/32/64-bit DDR2/3 up to 1,600Mbps and beyond with ECC option. Connectivity features include PCI-e Gen 2 controller, GE, 10GE, SGMII, RGMII, IEEE1588 Rev2 on all Ethernet ports, USB 2.0 – H/D, OTG, all with integrated PHY, USB 3.0, SATA ports and SDHC. The PacketPro family is manufactured on a 40nm TSMC® CMOS process and is available in both wire-bond and flip-chip packaging. The first PacketPro device begins sampling in November. More information about PacketPro can be founded at http://www.appliedmicro.com/products/process.html.

AppliedMicro Overview

AppliedMicro is a global leader in energy conscious computing solutions for telco, enterprise, data center, consumer and SMB applications. With a 30-year heritage as an innovator in high-speed connectivity and high performance embedded processing, AppliedMicro employs patented Power Architecture® SoCs to provide energy efficient products that can deliver up to a 40 percent reduction in power consumption without sacrificing performance. AppliedMicro’s corporate headquarters are located in Sunnyvale, California. Sales and engineering offices are located throughout the world. For further information regarding AppliedMicro, visit the company’s Web site at http://www.apm.com.

Applied Micro Circuits Corporation, AppliedMicro and the AppliedMicro logo are trademarks or registered trademarks of Applied Micro Circuits Corporation. The Power Architecture and Power.org word marks and the Power and Power.org logos and related marks are trademarks and service marks licensed by Power.org. All other product or service names are the property of their respective owners.

Photos/Multimedia Gallery Available: http://www.businesswire.com/cgi-bin/mmg.cgi?eid=6443789&lang=en

Source: Applied Micro Circuits Corporation

Read more: http://www.nasdaq.com/aspx/company-news-story.aspx?storyid=201009270800BIZWIRE_USPRX____BW5605#ixzz12IhFlfiz

 

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AMCC Taiwan Branch

十月 14, 2010
By

 

AMCC Products:
PowerPC

Relationship:
Distributor 

Telephone:
886-2-26558688 

Fax Number:
886-2-26555086 

Website:
http://www.memec.com/?cmd=location

Email:
Avnet.tw@avnet.com

 


Promate Electronic Co., LTD.

AMCC Products:
PowerPC, Communications

Relationship:
Distributor 

Telephone:
886-2-2659-0303 

Fax Number:
886-2-2659-3979 

Website:
http://www.promate.com.tw

Email:
sales@promate.com.tw

 

http://www.promate.com.tw/systemmodule/module.html

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AMCC Taiwan Branch
9F, No. 473, Sec.2, Ti-Ding Blvd.,
Neihu Dist., Taipei, 114 Taiwan
asiapac_sales@amcc.com
Tel: +886-2-2658-1732
Fax: +886-2-2658-1734

AMCC PACKetPRO MCORE

十月 1, 2010
By

 

image

image

PACKETpro™ is AppliedMicro’s second-generation of embedded multi-core processor SoCs and the first to feature expandability from one to eight 32-bit PowerPC 465 cores ranging in performance from 600 MHz to 1.5 GHz. Unlike any other multi-core available in the industry, the innovative SoC subsystem design features the Scalable Lightweight Intelligent Management processor (SLIMpro™) to enable breakthrough flexibility in power management, secure asymmetric multiprocessing (AMP), failover protection, resiliency and end-to-end security for a wide range of wired and wireless networking, multi-function printer, industrial, wireless access points and other mission critical embedded applications. Each device introduced into the PACKETpro™ family enables multiple operating system (OS) concurrencies while providing resource protection (processors, memory and I/O) for individual OSs so that each domain operates in a transparent, independent and protected mode. It also enables application-aware and usage-based power management to reduce and manage energy consumption. The multi-level crypto engines simultaneously offer line rate performance and investment protection against product cloning and hardware-software tampering.

Embedded Processors

The award-winning PowerPC 405 and 440 families have proven, best-in-class-technology and have achieved mass-market acceptance from major networking, storage and consumer OEMs. An extensive ecosystem of industry-leading partners provide operating systems, development tools, software platforms, board-level products, design services and technical training.

NEW PACKETpro™ family brochure

Learn More

NEW PowerPC EVALUATION KIT Family product brief

http://www.appliedmicro.com/products/Press+Release_APM_PacketPro_final.pdf

20101001

selection guide

http://www.appliedmicro.com/product-selector-guide/

packetpro

http://www.appliedmicro.com/products/apm_pp_web.pdf

 

http://www.appliedmicro.com/Embedded/

 

http://www.appliedmicro.com/Company/SynchromeshComputing_AMCC_OOB-Final-copyright.pdf

http://www.appliedmicro.com/

http://investor.appliedmicro.com/phoenix.zhtml?c=78121&p=irol-newsArticle&ID=1474906&highlight=

AppliedMicro PacketPro Multicore Processor Family Provides Intelligent SOC Management for Embedded Applications

September 27, 2010 — AppliedMicro (AMCC) today announced its next-generation PacketPro multicore processor family, designed with advanced subsystem and offload acceleration hardware to enable new levels of security, high availability, low latency, and power management for embedded applications.

PacketPro is AppliedMicro’s second-generation embedded processor SOC family and the first to feature off-load of critical features for multiple PowerPC processors with frequency capabilities ranging in performance from 600MHz to 2GHz and beyond. The SOC subsystem design features the Scalable Lightweight Intelligent Management processor or SLIMpro to enable breakthrough flexibility in SOC power management, protected asymmetric multiprocessing (PMP), failover protection, resiliency and end-to-end security for a wide range of mission-critical applications in wireless and wired networking, multi-function printer, industrial, access point markets.

Each device introduced into the PacketPro family enables multiple, concurrent operating systems (OS) while providing resource protection (processors, memory and I/O) that each domain operates in a transparent, independent and protected mode. It also enables application-aware and usage-based power management to reduce energy consumption. The multi-level crypto engine offers simultaneous wire-speed performance along with investment protection against product cloning and hardware-software tampering.

"PacketPro is an advanced SOC architecture that offers an ideal combination of high-performance and low power consumption at low cost," said Vinay Ravuri, Vice President and General Manager of AppliedMicro’s Processing Products Division. "Flexible power management enables deep sleep operating power of less than 200mW and includes Wake-on-LAN, USB, PCIe and others. With the ability to scale-down and turn off SOC resources when not in use and to scale-up to full power when system demands require, PacketPro provides developers unprecedented ability to dynamically control power-consumption levels."

AppliedMicro developed the PacketPro multicore SOC architecture specifically in response to developers’ need to manage abundant on-chip resources as the industry shifts from single core to multicore applications. These enhanced management capabilities help developers address the ongoing explosion in bandwidth, the growth of converged network applications and green energy initiatives. PacketPro also features configurable off-load engines for in-line packet processing, security, traffic classification, shaping and queue management to relieve the main processor complex.

"Simply adding more cores to a chip doesn’t necessarily solve the customer’s problem," said Linley Gwennap, principal analyst of The Linley Group. "AppliedMicro’s PacketPro is a well thought-out SOC architecture that addresses critical system-design issues such as end-to-end security, high availability, and flexible power management. The non-blocking multi-hub queuing fabric delivers a deterministic low-latency solution for packet processing."

The AppliedMicro PacketPro family features performance of up to 2GHz per core, 32kBytes L1 I/D and 256kBytes dedicated L2 cache per core, support for full symmetric multiprocessing (SMP) and ultra-flexible asymmetric multiprocessing (AMP). Memory and bus architecture supports 16/ 32/ 64-bit DDR2/3 up to 1,600Mbps and beyond with ECC option. Connectivity features include PCI-e Gen 2 controller, GE, 10GE, SGMII, RGMII, IEEE1588 Rev2 on all Ethernet ports, USB 2.0 – H/D, OTG, all with integrated PHY, USB 3.0, SATA ports and SDHC. The PacketPro family is manufactured on a 40-nm TSMC CMOS process and is available in both wire-bond and flip-chip packaging.

Availability

The first PacketPro device begins sampling in November.

Reprinted from SOCcentral.com, your first stop for ASIC, FPGA, EDA, and IP news and design information.
Copyright 2002 – 2009 Tech Pro Communications, P.O. Box 148, Jamison, PA 18929

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