PACKETpro™ is AppliedMicro’s second-generation of embedded multi-core processor SoCs and the first to feature expandability from one to eight 32-bit PowerPC 465 cores ranging in performance from 600 MHz to 1.5 GHz. Unlike any other multi-core available in the industry, the innovative SoC subsystem design features the Scalable Lightweight Intelligent Management processor (SLIMpro™) to enable breakthrough flexibility in power management, secure asymmetric multiprocessing (AMP), failover protection, resiliency and end-to-end security for a wide range of wired and wireless networking, multi-function printer, industrial, wireless access points and other mission critical embedded applications. Each device introduced into the PACKETpro™ family enables multiple operating system (OS) concurrencies while providing resource protection (processors, memory and I/O) for individual OSs so that each domain operates in a transparent, independent and protected mode. It also enables application-aware and usage-based power management to reduce and manage energy consumption. The multi-level crypto engines simultaneously offer line rate performance and investment protection against product cloning and hardware-software tampering.
The award-winning PowerPC 405 and 440 families have proven, best-in-class-technology and have achieved mass-market acceptance from major networking, storage and consumer OEMs. An extensive ecosystem of industry-leading partners provide operating systems, development tools, software platforms, board-level products, design services and technical training.
NEW PACKETpro™ family brochure
NEW PowerPC EVALUATION KIT Family product brief
AppliedMicro PacketPro Multicore Processor Family Provides Intelligent SOC Management for Embedded Applications
September 27, 2010 — AppliedMicro (AMCC) today announced its next-generation PacketPro multicore processor family, designed with advanced subsystem and offload acceleration hardware to enable new levels of security, high availability, low latency, and power management for embedded applications.
PacketPro is AppliedMicro’s second-generation embedded processor SOC family and the first to feature off-load of critical features for multiple PowerPC processors with frequency capabilities ranging in performance from 600MHz to 2GHz and beyond. The SOC subsystem design features the Scalable Lightweight Intelligent Management processor or SLIMpro to enable breakthrough flexibility in SOC power management, protected asymmetric multiprocessing (PMP), failover protection, resiliency and end-to-end security for a wide range of mission-critical applications in wireless and wired networking, multi-function printer, industrial, access point markets.
Each device introduced into the PacketPro family enables multiple, concurrent operating systems (OS) while providing resource protection (processors, memory and I/O) that each domain operates in a transparent, independent and protected mode. It also enables application-aware and usage-based power management to reduce energy consumption. The multi-level crypto engine offers simultaneous wire-speed performance along with investment protection against product cloning and hardware-software tampering.
“PacketPro is an advanced SOC architecture that offers an ideal combination of high-performance and low power consumption at low cost,” said Vinay Ravuri, Vice President and General Manager of AppliedMicro’s Processing Products Division. “Flexible power management enables deep sleep operating power of less than 200mW and includes Wake-on-LAN, USB, PCIe and others. With the ability to scale-down and turn off SOC resources when not in use and to scale-up to full power when system demands require, PacketPro provides developers unprecedented ability to dynamically control power-consumption levels.”
AppliedMicro developed the PacketPro multicore SOC architecture specifically in response to developers’ need to manage abundant on-chip resources as the industry shifts from single core to multicore applications. These enhanced management capabilities help developers address the ongoing explosion in bandwidth, the growth of converged network applications and green energy initiatives. PacketPro also features configurable off-load engines for in-line packet processing, security, traffic classification, shaping and queue management to relieve the main processor complex.
“Simply adding more cores to a chip doesn’t necessarily solve the customer’s problem,” said Linley Gwennap, principal analyst of The Linley Group. “AppliedMicro’s PacketPro is a well thought-out SOC architecture that addresses critical system-design issues such as end-to-end security, high availability, and flexible power management. The non-blocking multi-hub queuing fabric delivers a deterministic low-latency solution for packet processing.”
The AppliedMicro PacketPro family features performance of up to 2GHz per core, 32kBytes L1 I/D and 256kBytes dedicated L2 cache per core, support for full symmetric multiprocessing (SMP) and ultra-flexible asymmetric multiprocessing (AMP). Memory and bus architecture supports 16/ 32/ 64-bit DDR2/3 up to 1,600Mbps and beyond with ECC option. Connectivity features include PCI-e Gen 2 controller, GE, 10GE, SGMII, RGMII, IEEE1588 Rev2 on all Ethernet ports, USB 2.0 – H/D, OTG, all with integrated PHY, USB 3.0, SATA ports and SDHC. The PacketPro family is manufactured on a 40-nm TSMC CMOS process and is available in both wire-bond and flip-chip packaging.
The first PacketPro device begins sampling in November.
Reprinted from SOCcentral.com, your first stop for ASIC, FPGA, EDA, and IP news and design information.
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