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Products > FPGA
ECP3 IO Protocol Board (IOPB) Default Programming Files (version 1.2)
Updated: 03/25/11 – Updated: PAC design modified to check for the U1 DDR3 regulator being in a locked OFF state after a board power up, and if it is, to disable U1 briefly and then re-enable it.
Products > Intellectual Property – Lattice IP Cores and Reference Designs
IPUG60 SGMII and Gb Ethernet PCS IP Core User’s Guide (version 01.9)
Updated: 03/24/11 – Update document for new IP core version 3.4.
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