Altera FPGA I/F targets serial, high-density Bandwidth Engine device from MoSys

Altera FPGA I/F targets serial, high-density Bandwidth Engine device from MoSys–high-density-Bandwidth-Engine-device-from-MoSys?cid=NL_CommsDesign

Clive Maxfield  2/8/2011 10:02 AM EST

 Altera Corporation has announced that it has successfully completed interoperability testing between its Stratix IV GT FPGA and the Bandwidth Engine device from MoSys in a serial memory application.

Stratix IV GT FPGAs leverage the GigaChip Interface to interoperate with MoSys’s Bandwidth Engine device, providing designers of 100G wireline applications, such as traffic management and packet processing, a high-performance, high-bandwidth memory solution. With its Stratix IV GT FPGA, Altera is the first FPGA vendor to deliver device support for the GigaChip Interface.

Altera is a founding member of the MoSys GigaChip Alliance, which includes semiconductor companies collaborating to enable highly efficient serial chip-to-chip communications in next-generation, high-performance networking, computing and storage systems.

The GigaChip Interface leverages transceiver technology to deliver breakthrough chip-to-chip communications performance. MoSys utilized the Stratix IV GT FPGA in the development of the GigaChip Interface as a result of the timely availability of Altera’s high-performance transceiver technology.

“The GigaChip Interface represents a bandwidth density performance increase of 4X over DDR-type interfaces, while reducing system power and interface costs by 2X to 3X,”said David DeMaria, vice president of business operations at MoSys. “Our goal is to make it an open industry standard to enable highly efficient chip-to-chip communications, and we are pleased to announce the industry’s first interoperability with Altera. 

The transceiver technology featured in Stratix IV GT FPGAs provides MoSys an ideal platform for implementing the Bandwidth Engine interface and controller.

Altera’s proven transceiver technology combined with its Stratix IV GT FPGAs enables us to deliver to customers today a high-performance serial memory solution targeting next-generation networking systems.”

The GigaChip Interface is a short-reach, low-power serial interface, which enables highly efficient, high-bandwidth, low-latency performance. Stratix IV GT FPGAs support the GigaChip Interface through the device’s soft memory controller, which provide maximum design flexibility, and the device’s 11.3 Gbps transceivers. Supporting the GigaChip Interface within Stratix IV GT FPGAs enables customers to increase system performance, while minimizing board costs and pin counts.
“Incorporating the GigaChip Interface puts Altera in an exceptional position to address the market’s transition to 100G and beyond,” said Luanne Schirrmeister, senior director of component product marketing at Altera. “This interoperability demonstrates to wireline customers that we’re committed to delivering the highest performance solutions in the market.”

Stratix IV GT FPGAs are currently shipping in volume production.

Contact your Altera sales representative for pricing. Additional information regarding Stratix IV FPGAs can be found at

MoSys’s Bandwidth Engine devices are sampling now.

Additional information regarding the Bandwidth Engine and the GigaChip Interface can be found at



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