GC5330 Multi-Antenna Wideband Digital Transmit and Receive IC Solution


Multi-Antenna Wideband Digital Transmit and Receive IC Solution



The GC533x is a wideband transmit and receive signal processor that includes digital downconverter / upconverter (DDUC), transmit, receive, and capture buffer blocks. The transmit path includes crest factor reduction (CFR), digital predistortion (DPD) and associated feedback path, complex equalization, and bulk upconversion.

The receive path includes wideband and narrowband automatic gain control (AGC), bulk downconversion, complex equalization, and I/Q imbalance correction.

The DDUC section consists of four identical DDUC blocks, each supporting up to 12 channels. Each channel has independent fractional resamplers and NCOs to enable flexible carrier configurations. Multi-mode/multi-standard operation can be supported by configuring the individual DDUC blocks to different filtering and oversampling scenarios.

  • Integrated Transmit and Receive Digital IF Solution
  • Up to 4 TX, 8 RX, Plus DPD Feedback
  • TX-Transmit Includes DUC, CFR, DPD, TX Equalizer,
    and Bulk Upconverter
  • 62-MHz TX Signal Bandwidth With Fifth-Order DPD Correction
  • CFR: 6-dB PAR for WCDMA, 7-db LTE Signals With EVM Meeting 3GPP Specs;
    Configurable for All Major Wireless Infrastructure Standards
  • DPD: Memory Compensation, Typical ACLR Improvement of 20 dB or More
  • RX-Receive Includes DC-Offset Cancellation, Front-End and Back-End AGC,
    Bulk Downconverter, RX Equalizer, I/Q Imbalance Correction, DDC
  • 4 DDUCs, 1–12 Channels per DDUC, Each DDUC Can Be Programmed to
    TX or RX, at a Common Resampler Rate – Multimode Support
  • Seamless Interface to TI High-Speed Data Converters
  • 4 TX Aggregate Output to DACs up to 930 MSPS Complex
  • 8 RX Aggregate Input From ADCs up to 1.24 GSPS Real
  • Supports Envelope Tracking Techniques
  • 16-Tap (Complex) RX Equalizers
  • Two 4K Complex Word Capture Buffers for Signal Analysis,
    Adaptive Filtering, and DPD Algorithms
  • TMS320C6748 DPD Optimization Software
  • 1.1-V Core, 3.3-V I/O CMOS, 1.8-V I/O LVDS
  • Power Consumption, 3.5 W Typical
  • 484-Ball TE-PBGA Package, 23 mm × 23 mm
    • Multi-Standard Base Stations