Freescale adopts ARM cores in QorIQ line
Rick Merritt 6/19/2012 10:00 AM EDT
Freescale will add ARM cores to its Power-based QorIQ line next year, using a new modular architecture called that can be programmed in high-level languages such as C. SAN JOSE – Freescale will add next year two ARM-based families to its Power-based QorIQ line, using a new modular architecture called Layerscape. The architecture will sport ARM, Power and accelerator cores that can be programmed in high-level languages such as C.
The news comes at a time when communications systems makers say chip vendors need to speed time-to-market by easing the complexity of their work creating value-added software. To date, software for Freescale’s QorIQ chips, and many of its competitors, are programmed in assembly languages, some of the work done on a custom basis by the chip vendor.
The trend toward easier programmability has been driving a move to general-purpose cores. Intel has been gaining share in comms systems for several years, riding this trend. More recently, LSI Corp. announced it will migrate from PowerPC to ARM cores in its base station SoCs.
Freescale aims to differentiate itself by offering a menu of both general purpose ARM and Power cores along with a new set of packet-processing accelerators all programmable in C/C++. T
he first two families of the Layerscape chips will sample in mid-2013 when the new software programming environment should be ready.
“There will be a small compromise [in performance to move from assembler to high-level languages] but I think it’s much more important to focus on time-to-market to help [OEM] customers differentiate themselves,” said Bernd Lienhard, general manager of the Freescale’s networking processor group.
Today’s chips have plenty of performance to take up at least some of the slack, he said. On the other hand, programming for the packet processing blocks in QorIQ’s chips is so complex the Freescale currently does the work itself.
“If [OEMs] want to change anything they have to come to Freescale to do it, and it takes longer,” said Lienhard.
Freescale has plenty of work to execute on its plan.
The company must create a software environment that straddles both the big endian Power and little endian ARM architectures. In addition, it aims to replace existing state machine blocks used to accelerate packet forwarding operations with C-programmable blocks, probably built on custom variations of Power or ARM cores, Freescale is not yet ready to discuss.
ARM will not replace Power cores for Freescale, at least in the foreseeable future. The company said it has long-term plans to continue designing and supporting Power cores.
The ARM cores help Freescale reach “into the low end where we traditionally have not been able to play, so I would look at this as an expansion,” said Lienhard.
Specifically, Freescale will use ARM Cortex-A7 cores to deliver a sub-3W SoC and an A15 to power a 5W chip. Both are set to sample in mid-2013. Power-based chips will provide higher-end performance than the ARM cores are likely to reach in the near term and may also be the basis for programmable packet-accelerator blocks.
“You will see the Power architecture for a long time–it will co-exist for a decade-plus,” he said. The company has made no change in the resources it puts behind Power cores, and “we are still going to refine existing Power cores [because] we see Power has a strong base in this sector,” he added.
Nevertheless, companies such as Freescale will find it increasingly difficult to justify developing its own PowerPC processor cores. In this way, the smaller Power ecosystem will come under pressure over time as the battle between Intel and ARM cores intensifies on all fronts including the comms space.
In the short term, Freescale has a deep and broad investment in Power. In February, it described its latest Power core, the Power e6500, and new SoCs using it. The core surpassed all competitors in some benchmarks, Freescale said.
Specifically, Freescale announced two ARM-based QorIQ chips it will deliver in mid-2013.
The LS-1 family uses two ARM Cortex-A7 cores running at up to 1.2 GHz in a sub-3W embedded processor.
The LS-2 family features two ARM Cortex-A15 cores running at up to 1.5 GHz and under 5W total power.
Targeted applications include residential gateways, enterprise access points, smart energy systems, industrial communications, line cards and robotics.
The deal marks the second big design win for ARM in as many weeks. Last week, AMD said it will use ARM cores for security blocks in a future line of its processors.