MPXS2010/3020
Power Architecture® MCUs for Safety Applications
http://www.ebv.com/index.php?id=162&ct_ref=u1007&tx_ebvproductfe_pi1%5Buid%5D=3713
The PXS20 and PXS30 are 32-bit Power Architecture microcontrollers for a range of industrial, medical, and transportation safety critical applications.
All devices in this family are built around a dual core platform with an innovative safety concept that reduces system cost and effort for the customer to achieve IEC61511 or IEC61508 certification of their systems.
PXS20 and PXS30 devices can operate in a lock step mode (LSM) and/ or decoupled parallel mode (DPM), selected at power-on reset time.
The LSM allows reaching the highest safety level, IEC61508 SIL3, with minimum software overhead.
It has been defined to allow reaching IEC61508 SIL3 level with minimum software overhead.
Devices’ sphere of replication (SoR) refers to a set of replicated key modules where at the outputs a formal hardware check is performed to ensure that the same operations or transactions are executed on a clock-per-clock basis.
A presence of redundancy checkers (RC) at the outputs of the SoR for the peripheral bus, the Flash memory subsystem and the SRAM subsystem represents a minimum guarantee that non-common cause faults are detected when the two channels redundantly are merged into a single actuator or recipient.
In decoupled parallel mode, each CPU core and connected channel run independently from the other one and redundancy checkers (RC) are disabled.
The DPM mode increased performance can be estimated as about 1.6× the performance of the LSM mode at the same clock frequency.
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