Xilinx Announces ISE Design Suite 13.4
Further Extending 7 Series FPGA Support and Design Productivity
Latest release includes the New MicroBlaze Micro Controller System, Enhanced Debug with 2D Eye Scan and Partial Reconfiguration Support for Artix-7 and Virtex-7 XT FPGAs
SAN JOSE, Calif., Jan. 18, 2012 /PRNewswire/ — Xilinx, Inc. (NASDAQ: XLNX) today released ISE® Design Suite 13.4, which provides public access to the MicroBlaze™ Micro Controller System (MCS), new RX Margin Analysis and debug capabilities for the 28nm 7 Series FPGAs and partial reconfiguration support for the Artix™-7 family and Virtex®-7 XT devices.
MicroBlaze MCS Simplifies Microcontroller-based Designs
MicroBlaze MCS, new to the Xilinx® LogiCORE™ IP core offering, provides a turnkey microcontroller solution to Xilinx customers. It includes the MicroBlaze processor, local memory for program and data storage, as well as tightly coupled GPIO, timers, interrupt controllers and other standard peripherals.
MCS is supported across a broad range of Xilinx FPGA families, and is pre-configured for easy deployment by hardware developers. Software developers will find familiar tools including the Xilinx Software Development Kit (SDK), command line gcc, Xilinx Microprocessor Debugger (XMD) and the same standard MicroBlaze API used by larger processor configurations. Hardware developers will appreciate that the MicroBlaze processor and all Xilinx embedded IP cores are now supported with the Synopsys VCS simulator in addition to Cadence, Mentor and Xilinx simulation solutions. The MicroBlaze MCS is included in all ISE Design Suite Editions, ISE WebPACK and is compatible with AutoESL™ high-level synthesis tool v2011.4.
New RX Margin Analysis Tool
The ChipScope™ Pro tool, available in the ISE 13.4 release, now provides an RX Margin Analysis tool to help engineers optimize signal quality and lower the bit error ratio (BER) on their designs. The RX Margin Analysis tool uses 2-dimensional statistical Eye Scan algorithms to interactively characterize and optimize channel quality in real time, or during post-run processing.
4th Generation Partial Reconfiguration
Partial reconfiguration support for Artix-7 and Virtex-7 XT FPGAs is now available in the PlanAhead™ tool. Partial reconfiguration dynamically modifies logic blocks while the remaining logic operates without interruption. This means designers can use Artix-7 and Virtex-7 XT devices to build flexible systems that are able to swap functions and perform remote updates while operational. Partial reconfiguration also allows designers to reduce costs and design size by taking advantage of time-multiplexing that ultimately leads to reduced board space and minimizes bitstream storage because smaller, or fewer, devices can be utilized. Smaller and fewer devices can also lead to reductions in system power, while swapping out power hungry tasks can minimize the FPGA’s dynamic power consumption. This marks the first time Xilinx is offering partial reconfiguration for an entire generation of FPGA families from low-cost to high-end.
“With hardware designs increasingly using more point-to-point buses, at faster speeds and sending larger data packets, it is becoming more important for design engineers to pay close attention to the quality, error rates and margins that such designs require,” said Tom Feist, Senior Director of Software and Tools Marketing at Xilinx. “Increasing designer productivity continues to be the top focus for Xilinx. ISE Design Suite 13.4 further extends and simplifies our development tools to ensure their ease of use and support in deploying our entire 7 series FPGA families in these types of designs.”
Extends Support for 7 Series FPGAs
ISE Design Suite 13.4 is the first public release supporting the Artix-7 and Virtex-7 XT FPGA families.
The Artix-7 FPGA delivers the lowest power and lowest cost to address high-volume markets including: consumer 3DTV, multifunction printers, digital SLR cameras, automotive driver assistance and infotainment, low power handheld communications, medical endoscopes and handheld ultrasound devices and industrial system monitor and control. With Agile Mixed Signal (AMS) capabilities, included in all 28nm Xilinx devices, designers have the industry’s most flexible general purpose analog interface for customizing a wide variety of applications, from simple control and sequencing to more signal processing intensive tasks like linearization, calibration, and filtering.
Virtex-7 XT devices offer the highest processing bandwidth with high performance transceivers, digital signal processing (DSP) and BRAM. These devices integrate an unprecedented up to 96 10G Base KR backplane-capable serial transceivers, provide 5.3 TMACs of DSP, 67 Mbits of internal memory and more than 1M logic cells. The Virtex-7 XT family utilizes Xilinx’s revolutionaryStacked Silicon Interconnect (SSI) technology, allowing multiple die to be combined in a single chip, and provides a 100x improvement in inter-die bandwidth per watt compared to multi-chip approaches.
PlanAhead Tool Extends User Productivity
The Xilinx ISE PlanAhead Design and Analysis Tool is a comprehensive development environment for design creation, analysis, planning and implementation. The PlanAhead tool accelerates time to production with a unique integrated front-to-back environment that includes design analysis at each phase of the design cycle – RTL development, IP integration, verification, synthesis and place and route. The end result is rapid convergence on power consumption, resource utilization and performance with fewer time-consuming design iterations. Up front design analysis and design preservation flows that ensure timing from run to run are critical for customers targeting the new 7 series devices.
The PlanAhead tool now provides public access for Xilinx 7 series FPGAs with productivity improvements to assist users in closing their designs, intelligent clock gating to reduce power, team design flows and fifth-generation partial reconfiguration technology now offered for Artix-7 FPGAs and Virtex-7 XT FPGAs to enable fewer or smaller devices, reduce power and improve system upgradability.
Availability and Pricing
ISE Design Suite 13 is available now for all ISE Editions and list priced starting at $2,995 for the Logic Edition and now supports 32 and 64 bit Windows 7 operating systems.
Customers can download full-featured 30-day evaluation versions at no charge from the Xilinx web site.
Please visit the ISE Design Suite 13 website to get started today with the ISE Design Suite 13 software release or for more information about the power and cost-saving design methodologies and productivity innovations introduced in ISE Design Suite 13.